- Use the PMAP_ASID_* constants from pmap.h
- Track pmap_pvo_{enter,remove}() depth in the same way as mpc6xx's pmap
(on which this pmap was originally based).
- Some misc. tidying up and added commentary.
- Use the VA/KVA to select whether to use the IPT or PTEG instead of
checking which pmap is being operated on.
- Add a handy DDB-callable function which will scan the kernel IPT
looking for inconsitencies.
- Finally, when unmapping a pool page, purge the data cache for the
page. This permits write-back caching to be enabled for kernel
text/data.
machine-specific code.
- Re-work the code which detects a nested critical section event.
We can now determine who is the owner of the critical section, and
what event occurred while it was owned.
- Work-around a silicon bug which can cause a nested critical event.
In the _EXCEPTION_ENTRY() macro (which sets up the critical section),
if there is a pending hardware interrupt which has a higher priority
than the current IMASK, then the "putcon" which supposedly clears SR.BL
and sets SR.IMASK to 0xf is not atomic. The pending hardware interrupt
will be taken, causing a nested critical section event. The work-around
is to update SR.BL and SR.IMASK separately using two "putcon" insns.
- Make it possible to at least *try* to resume execution if we
get an NMI.
- Major clean-up of the panic/critical section trap handlers.
The dumped state is now much more accurate.
to const BF_KEY * vars, and I chose to ``fix'' it in this file
rather than elsewhere in the framework because, although the other
fix was more appropriate, nothing seems to use the code in this
file and hence the risk of disrupting other people was lower. In
the future, the more appropriate change would be to change blowfish.h
and bf_enc.c to have functions with signatures:
BF_encrypt(BF_LONG *, const BF_KEY *);
BF_decrypt(BF_LONG *, const BF_KEY *);
so the register is correctly sign-extended.
- Some comment fixes.
- Restore the FP state from the sigcontext if FP regs were saved.
- Fix up r0 for the benefit of the syscall stub.
This merge changes the device switch tables from static array to
dynamically generated by config(8).
- All device switches is defined as a constant structure in device drivers.
- The new grammer ``device-major'' is introduced to ``files''.
device-major <prefix> char <num> [block <num>] [<rules>]
- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.
- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.
- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.
- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.
- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.
.MAIN must be defined for the implicit target rule to kick in
this fixes compilation with call like 'make', i.e. without specified target
another option would be to move the .if make() condition after config(8)
generated goo, since config(8) implicitly generates a .MAIN: directive too,
but the MD .if make() really belongs into (7) misc settings section IMHO
If a segment starts exactly at 16M don't try to split it because that causes
the code to try to call uvm_page_physload with a zero length segment.
(kern/17199)
- Set up a Panic Stack,
- Don't pre-map the sysfpga at this time.
- Calculate the CPU speed only if SH5_CPU_SPEED isn't defined.
- On a related note, make the CPU speed probing code more accurate.
- Print the CPU speed at startup.
- Force RB_SINGLE for now, at least until I get a bootloader written.
back-end to indicate that the device always sees reads as 32-bit
transactions, even if the host does 8 or 16-bit reads.
This is necessary for the SH-5 "Cayman" on-board ethernet. The SMsC part
is behind an FPGA which maps all cpu reads to 32-bits transactions.
- in _EXCEPTION_EXIT, copy the current ASID to the pre-exception
context before we switch.
- fix the pteg hash generation code and EPN masking in the tlb
miss handler.
Sprinkle some DIAGNOSTIC checks.
to ensure the callee-saved set will be restored when we switch to it.
(It doesn't actually matter to the new process; it just inherits some
crud in those registers from the kernel if we don't set the bit).
Also ensure the strings pointer in r7 is sign-extended.
previously to note that they reference the RCS ID in "pcmciadevs".
Hence, committed versions which incorrectly pointed back to the RCS ID
of the "pcmciadevs" that existed prior to my addition. Corrected in this
commit.
already support under another name:
wi0 at pcmcia0 function 0: NETGEAR MA401RA Wireless PC, Card, ISL37300PEval-RevA
wi0: 802.11 address <whatever>
wi0: using RF:PRISM2.5 MAC:ISL3873B(PCMCIA)
wi0: Intersil Firmware: Primary (1.0.7), Station (1.3.6)
Seems that we assume that the dram blocks are sorted, and that the first/lowest address is also where the kernel is.
If the above is not true, then we're on a kinetic (probably should make a better way to indicate this) So search for all dram blocks < with starting addr lower than the first block and remove them.
Currently there's minimal performance gain (which is odd as the SDRAM is meant to be faster, I'm wondering if we need to prod some hidden registers to set timing information.
Note that I still get 16MB/s compared with 7MB/s on RiscStation and 93MB/s on my cats. I'm thinking that something else is seriously nasty on acorn32.
- aging ang clear inactivity stations
- DTIM field in beacon/probe response.
- ignore IFF_PROMISC for hostap mode, since 802.11 has 3 address fields,
so that promisc mode is not required for AP function.
any time we remove all access to a given virtual page,
we must invalidate the (write-through) L1 dcache.
pmap_remove() still had it, but pmap_kremove(), pmap_clear_reference()
and pmap_page_protect(VM_PROT_NONE) didn't and needed it.
fixes PR 18040.
section of another exception. This is likely to happen if the kernel
stack is misaligned, has dropped off the bottom of the PCB, or has
otherwise gone into orbit.
In this case, switch to a safe stack, save as much of the machine
state as possible and dump it to the console.
accessing the kernel stack, since a TLB miss on the kernel stack
will result in r24 being trashed.
Also clear the ES_CRITICAL flag just before returning to the
previous context.
/dev/ttyS0 crashed the kernel. This is because sacom_filltx uses some
uninitialized static variables. Pulling the salues from softc instead
fixes the problem (this is what was done before the drver was moved
from /sys/arch/hpcarm to /sys/arch/arm, anyway).
remove a test that has been obsoleted by the authentication failure
counter - enter slow retry mode always, not only if we already transfered
data successfully (the test was designed to disable retries when the
initial authentication setting was not correct, the auth failure counter
does this job better).
we don't know anything about with a PADT packet.
Use with care, this is pretty dangerous and will kill all userland PPPoE
implementations. Therefore it is not enabled by default nor added as
a commented out option to GENERIC kernels.
But it is highly usefull if you have a fixed IP, an ISP that does not use
LCP echo requests for link monitoring and you want to recover quickly after
a crash or otherwise ungracefull disconnect.
as intrframe and trapframe are concerned.
According to the ABI, only the low 32-bits of these registers are
guaranteed to be preserved by the callee. Therefore, we need to
preserve all 64-bits of them in the interrupt trampoline.
ToDo:
- Symbol support (can't test as yet, due to lack of symbols),
- Take notice of adjacent "movi/shori" instructions in order to display
the resulting 32/64-bit value, with symbol lookup if possible.
At the very least, this will dump the machine state. At best,
we get into ddb().
This provides a useful way to regain control using an NMI button
if the cpu decides to spin at a high ipl.
scw