Add a few more cpu-specific cacheop functions.
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scw
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7fa549e8d4
commit
0d7cafd74b
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@ -1,4 +1,4 @@
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/* $NetBSD: cacheops.h,v 1.1 2002/07/05 13:31:56 scw Exp $ */
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/* $NetBSD: cacheops.h,v 1.2 2002/09/10 11:56:32 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -38,7 +38,10 @@
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#ifndef __SH5_CACHEOPS_H
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#define __SH5_CACHEOPS_H
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extern void (*__cpu_cache_purge)(vaddr_t, vsize_t);
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extern void (*__cpu_cache_invalidate)(vaddr_t, vsize_t);
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extern void (*__cpu_cache_dpurge)(vaddr_t, vsize_t);
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extern void (*__cpu_cache_dpurge_iinv)(vaddr_t, vsize_t);
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extern void (*__cpu_cache_dinv)(vaddr_t, vsize_t);
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extern void (*__cpu_cache_dinv_iinv)(vaddr_t, vsize_t);
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extern void (*__cpu_cache_iinv)(vaddr_t, vsize_t);
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#endif /* __SH5_CACHEOPS_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: stb1_locore.S,v 1.5 2002/09/04 13:58:36 scw Exp $ */
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/* $NetBSD: stb1_locore.S,v 1.6 2002/09/10 11:56:33 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -68,16 +68,14 @@
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* virtual address space until pmap_bootstrap has been called.
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*/
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Lsh5_stb1_init:
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addz.l r2, r63, r2 /* Clear the upper 32-bits of r2 */
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movi 2, r1
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add.l r2, r63, r2 /* Sign-extend the upper 32bits of r2 */
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movi 3, r1 /* Inv/Enable the Caches */
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LDC32(0x01600000, r0) /* Instruction Cache Control Register */
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putcfg r0, 0, r1 /* Invalidate instruction cache */
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putcfg r0, 0, r1 /* Inv & Enable instruction cache */
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putcfg r0, 1, r63
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synci
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LDC32(0x01e00000, r0) /* Operand Cache Control Register */
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putcfg r0, 0, r1 /* Invalidate operand cache */
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putcfg r0, 0, r1 /* Inv & Enable operand cache */
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putcfg r0, 1, r63
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synco
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pta/u 1f, tr0 /* Pre-load branches */
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LDC32(0x00800000 + (16 * 63), r0) /* Top of DTLB */
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@ -95,12 +93,12 @@ Lsh5_stb1_init:
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putcfg r1, 0, r63
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/* Fix up KSEG0 physical page and attributes in ITLB */
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movi SH5_PTEL_CB_NOCACHE | SH5_PTEL_SZ_512MB | SH5_PTEL_PR_X, r3
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movi SH5_PTEL_CB_WRITEBACK | SH5_PTEL_SZ_512MB | SH5_PTEL_PR_X, r3
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or r2, r3, r3
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putcfg r1, 1, r3
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/* Ditto for DTLB */
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movi SH5_PTEL_CB_NOCACHE | SH5_PTEL_SZ_512MB | SH5_PTEL_PR_R | SH5_PTEL_PR_W, r3
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movi SH5_PTEL_CB_WRITEBACK | SH5_PTEL_SZ_512MB | SH5_PTEL_PR_R | SH5_PTEL_PR_W, r3
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or r2, r3, r3
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putcfg r0, 1, r3
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@ -114,8 +112,8 @@ Lsh5_stb1_init:
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putcfg r1, 0, r2
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/*
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* The TLB is primed, the cache is clean. All we have to do now
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* is enable the MMU and FPU before returning to the caller.
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* The TLB is primed, the cache is clean and enabled. All we have
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* to do now is enable the MMU and FPU before returning to the caller.
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*/
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getcon sr, r0
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LDUC32(SH5_CONREG_SR_ASID_MASK << SH5_CONREG_SR_ASID_SHIFT, r1)
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@ -155,12 +153,11 @@ Lsh5_stb1_init:
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*/
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ENTRY_NOPROFILE(_sh5_stb1_tlbinv)
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getcon sr, r5
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LDC32(SH5_CONREG_SR_BL, r4)
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ori r2, SH5_PTEH_V, r2 /* Only check valid entries */
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ori r3, SH5_PTEH_V, r3
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addz.l r2, r63, r2 /* Zero-extend PTEH */
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addz.l r3, r63, r3 /* Zero-extend PTEL */
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or r4, r5, r4 /* Block exceptions */
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ori r5, SH5_CONREG_SR_IMASK_ALL, r4 /* Block interrupts */
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putcon r4, sr
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ptabs/u r18, tr1 /* Get return address to tr1 */
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@ -195,7 +192,7 @@ ENTRY_NOPROFILE(_sh5_stb1_tlbinv)
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addi r0, 16, r0 /* Next ITLB entry */
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bge/l r1, r63, tr0 /* Back if not done and not found */
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putcon r5, sr /* Re-enable exceptions */
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putcon r5, sr /* Restore interrupt mask */
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blink tr1, r63
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@ -313,18 +310,27 @@ ENTRY_NOPROFILE(_sh5_stb1_tlbinv_cookie)
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*
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* Callable from C code.
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*
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* Invalidate all instruction and data TLB entries (except [DI]TLB#0,
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* which maps the kernel in KSEG0).
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* Invalidate all instruction and data TLB entries with non-zero ASIDs.
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*/
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ENTRY_NOPROFILE(_sh5_stb1_tlbinv_all)
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pta/u 1f, tr0 /* Pre-load branches */
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ptabs/u r18, tr1 /* Get return address to tr1 */
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LDC32(0x00800000 + (16 * 63), r0) /* DTLB Top */
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movi (16 * 63), r1 /* ITLB Top */
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1: putcfg r0, 0, r63 /* Invalidate DTLB entry */
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movi (SH5_PTEH_ASID_MASK << SH5_PTEH_ASID_SHIFT), r2
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1: getcfg r0, 0, r3 /* Fetch DTLB entry */
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and r3, r2, r4 /* Keep ASID */
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cmvne r4, r63, r3 /* If ASID != 0, clear r3 */
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putcfg r0, 0, r3 /* Invalidate DTLB entry */
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addi r0, -16, r0 /* Next DTLB slot */
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getcfg r1, 0, r3 /* Fetch ITLB entry */
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and r3, r2, r4 /* Keep asid */
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cmvne r4, r63, r3 /* If ASID != 0, clear r3 */
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putcfg r1, 0, r63 /* Invalidate ITLB entry */
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addi r1, -16, r1 /* Next ITLB slot */
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bne/l r1, r63, tr0 /* Back until all checked */
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blink tr1, r63
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@ -439,28 +445,76 @@ ENTRY_NOPROFILE(_sh5_stb1_tlbload)
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/******************************************************************************
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*
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* void _sh5_stb1_cache_purge(vaddr_t start, vsize_t len)
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* void _sh5_stb1_cache_dpurge(vaddr_t start, vsize_t len)
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*/
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ENTRY_NOPROFILE(_sh5_stb1_cache_purge)
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ENTRY_NOPROFILE(_sh5_stb1_cache_dpurge)
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pta/l 1f, tr0
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ptabs/l r18, tr1
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add r2, r3, r3
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1: ocbp r2, 0
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addi r2, 32, r2
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addi r3, -32, r3
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bgt/l r3, r63, tr0
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bgtu/l r3, r2, tr0
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synco
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synci
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blink tr1, r63
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/******************************************************************************
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*
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* void _sh5_stb1_cache_invalidate(vaddr_t start, vsize_t len)
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* void _sh5_stb1_cache_dpurge_iinv(vaddr_t start, vsize_t len)
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*/
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ENTRY_NOPROFILE(_sh5_stb1_cache_invalidate)
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ENTRY_NOPROFILE(_sh5_stb1_cache_dpurge_iinv)
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pta/l 1f, tr0
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ptabs/l r18, tr1
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add r2, r3, r3
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1: ocbp r2, 0
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icbi r2, 0
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addi r2, 32, r2
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bgtu/l r3, r2, tr0
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synco
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synci
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blink tr1, r63
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/******************************************************************************
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*
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* void _sh5_stb1_cache_dinv(vaddr_t start, vsize_t len)
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*/
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ENTRY_NOPROFILE(_sh5_stb1_cache_dinv)
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pta/l 1f, tr0
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ptabs/l r18, tr0
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add r2, r3, r3
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1: ocbi r2, 0
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addi r2, 32, r2
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addi r3, -32, r3
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bgt/l r3, r63, tr0
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bgtu/l r3, r2, tr0
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synco
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synci
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blink tr0, r63
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/******************************************************************************
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*
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* void _sh5_stb1_cache_dinv_iinv(vaddr_t start, vsize_t len)
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*/
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ENTRY_NOPROFILE(_sh5_stb1_cache_dinv_iinv)
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pta/l 1f, tr0
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ptabs/l r18, tr0
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add r2, r3, r3
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1: ocbi r2, 0
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icbi r2, 0
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addi r2, 32, r2
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bgtu/l r3, r2, tr0
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synco
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synci
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blink tr0, r63
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/******************************************************************************
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*
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* void _sh5_stb1_cache_iinv(vaddr_t start, vsize_t len)
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*/
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ENTRY_NOPROFILE(_sh5_stb1_cache_iinv)
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pta/l 1f, tr0
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ptabs/l r18, tr0
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add r2, r3, r3
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1: icbi r2, 0
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addi r2, 32, r2
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bgtu/l r3, r2, tr0
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synci
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blink tr0, r63
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@ -1,4 +1,4 @@
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/* $NetBSD: stb1var.h,v 1.1 2002/07/05 13:32:07 scw Exp $ */
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/* $NetBSD: stb1var.h,v 1.2 2002/09/10 11:56:33 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -44,7 +44,10 @@ extern void _sh5_stb1_tlbinv(pteh_t, pteh_t);
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extern void _sh5_stb1_tlbinv_cookie(pteh_t, u_int);
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extern void _sh5_stb1_tlbinv_all(void);
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extern void _sh5_stb1_tlbload(void);
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extern void _sh5_stb1_cache_purge(vaddr_t, vsize_t);
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extern void _sh5_stb1_cache_invalidate(vaddr_t, vsize_t);
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extern void _sh5_stb1_cache_dpurge(vaddr_t, vsize_t);
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extern void _sh5_stb1_cache_dpurge_iinv(vaddr_t, vsize_t);
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extern void _sh5_stb1_cache_dinv(vaddr_t, vsize_t);
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extern void _sh5_stb1_cache_dinv_iinv(vaddr_t, vsize_t);
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extern void _sh5_stb1_cache_iinv(vaddr_t, vsize_t);
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#endif /* _STB1VAR_H */
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