useful should one occur.
- Manually poke some config values into the sh5pci host bridge's
config registers since it doesn't appear in config. space.
- Reserve the first 256 bytes of i/o space to avoid assigning i/o
address 0 to any cards.
- Slight tweak to the initialisation code after consultation with
SuperH and the linux driver.
map accurately tracks the same flag in the segments belonging to it.
The map's copy can be set only if all the segments are coherent.
This finally gets NFS writes fully working on my PCI ex(4) card.
- Track unmanaged mappings of RAM more closely by allocating a pvo
for them. This allows us to check more accurately for multiple
cache-mode-incompatible mappings.
- As part of the above, implement pmap_steal_memory(). This has the
beneficial side-effect of moving a fair chunk of kernel data
structures into KSEG0.
pretty much working, at least for non-NFS use.
With NFS, it fails under pressure probably due to operand cache aliases
between KSEG0 and regular 4KB mappings elsewhere. Sigh.
operand cache synonyms and paradoxes for shared mappings:
- Writable mappings are cache-inhibited if the underlying physical
page is mapped at two or more *different* VAs.
This means that read-only mappings at different VAs are still
cacheable. While this could lead to operand cache synonyms, it
won't cause data loss. At worst, we'd have the same read-only
data in several cache-lines.
- If a new cache-inhibited mapping is added for a page which has
existing cacheable mappings, all the existing mappings must be
made cache-inhibited.
- Conversely, if a new cacheable mapping is added for a page which
has existing cache-inhibited mappings, the new mapping must also
be made cache-ibhibited.
- When a mapping is removed, see if we can upgrade any of the
underlying physical page's remaining mappings to cacheable.
TODO: Deal with operand cache aliases (if necessary).
of the loadable sections to correspond to the physical address of
RAM in the Cayman. This is so sh5gdb uploads the image to the correct
place. (Should've done this ages ago instead of manually running a
script...)
This can be removed when I get a native bootloader written.
cacheable attribute of a mapping.
- Honour PMAP_NC in pmap_enter() using NOCACHE, instead of DEVICE.
- No longer need to re-fetch the ptel in pmap_pa_unmap_kva() as
syncing the cache no longer risks causing a TLB miss.
- Re-define bus_size_t and bus_addr_t to be u_int32_t.
While this may well lose for future silicon with NEFFBITS > 32, the
original u_long was a waste on current designs (especially for _LP64).
Allocate/Prefetch one cache-line ahead of the one we're about to deal with.
This reduces the chances of the cpu stalling while waiting for the cache
to flush a dirty line in order to satisfy the Allocate/Prefetch request.
registers in any trap/interrupt exception frame found.
- Slight tweak to more accurately detect the correct call-site when
looking for a function's prologue.
