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The FP status register is 32-bits wide, so don't use register_t in

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the various state frames.
This commit is contained in:
scw 2002-09-28 11:03:08 +00:00
parent 58931592a1
commit 4d809d551d
3 changed files with 11 additions and 9 deletions
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5
sys/arch/sh5/include/frame.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: frame.h,v 1.5 2002/09/02 14:00:26 scw Exp $ */
/* $NetBSD: frame.h,v 1.6 2002/09/28 11:03:08 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -152,7 +152,8 @@ struct trapframe {
* by the FPRS bits of the USR register, saved in switchframe->sf_usr.
*/
struct fpregs {
register_t fpscr;
u_int32_t fpscr;
u_int32_t pad;
register_t fp[32];
};

5
sys/arch/sh5/include/reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: reg.h,v 1.1 2002/07/05 13:32:01 scw Exp $ */
/* $NetBSD: reg.h,v 1.2 2002/09/28 11:03:08 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -46,7 +46,8 @@ struct reg {
register_t r_tr[8];
register_t r_fpscr;
u_int32_t r_fpscr;
u_int32_t r_pad;
register_t r_fpregs[32];
};

10
sys/arch/sh5/sh5/cpu_switch.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu_switch.S,v 1.9 2002/09/10 12:06:49 scw Exp $ */
/* $NetBSD: cpu_switch.S,v 1.10 2002/09/28 11:03:09 scw Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -141,7 +141,7 @@
FPSV(pcb,PCB_CTX_FPREGS_DR56,dr56,dr58,dr60,dr62) ;\
fmov.dq dr0, r0 /* Save dr0 temporarily */ ;\
fgetscr fr0 /* Always save FPSCR */ ;\
fst.d pcb, PCB_CTX_FPREGS_FPSCR, dr0 ;\
fst.s pcb, PCB_CTX_FPREGS_FPSCR, fr0 ;\
fmov.qd r0, dr0 /* Restore dr0 */ ;\
99:
@ -199,7 +199,7 @@
andi r0, 1, r0 ;\
bne/u r0, r63, tr0 /* Skip FP restore if FPU disabled */ ;\
fmov.dq dr0, r0 /* Save dr0 temporarily */ ;\
fld.d pcb, PCB_CTX_FPREGS_FPSCR, dr0 ;\
fld.s pcb, PCB_CTX_FPREGS_FPSCR, fr0 ;\
fputscr fr0 /* Always restore the FPSCR */ ;\
fmov.qd r0, dr0 /* Restore dr0 */ ;\
andi mdf, MDP_FPSAVED, r0 /* Skip if FP state wasn't saved */ ;\
@ -520,7 +520,7 @@ ENTRY(sh5_fpsave)
FPSV(r3,PCB_CTX_FPREGS_DR56,dr56,dr58,dr60,dr62)
fmov.dq dr0, r0 /* Save dr0 temporarily */
fgetscr fr0 /* Always save FPSCR */
fst.d r3, PCB_CTX_FPREGS_FPSCR, dr0
fst.s r3, PCB_CTX_FPREGS_FPSCR, fr0
fmov.qd r0, dr0 /* Restore dr0 */
blink tr1, r63
@ -539,7 +539,7 @@ ENTRY(sh5_fprestore)
andi r0, 1, r0
bne/u r0, r63, tr1 /* Skip FP save if FPU disabled */
fmov.dq dr0, r0 /* Save dr0 temporarily */
fld.d r3, PCB_CTX_FPREGS_FPSCR, dr0
fld.s r3, PCB_CTX_FPREGS_FPSCR, fr0
fputscr fr0 /* Always restore FPSCR */
fmov.qd r0, dr0 /* Restore dr0 */
FPRS(r3,PCB_CTX_FPREGS_DR0,dr0,dr2,dr4,dr6)