- Hook the PCI arbiter and error interrupts, and print something
useful should one occur. - Manually poke some config values into the sh5pci host bridge's config registers since it doesn't appear in config. space. - Reserve the first 256 bytes of i/o space to avoid assigning i/o address 0 to any cards. - Slight tweak to the initialisation code after consultation with SuperH and the linux driver.
This commit is contained in:
scw
parent
5dded94793
commit
26ebb442bf
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@ -1,4 +1,4 @@
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/* $NetBSD: sh5_pci.c,v 1.5 2002/10/02 15:52:37 thorpej Exp $ */
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/* $NetBSD: sh5_pci.c,v 1.6 2002/10/04 10:22:24 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -158,6 +158,7 @@ static int sh5pci_intr_dispatch(void *);
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static void sh5pci_bridge_init(struct sh5pci_softc *);
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static int sh5pci_check_master_abort(struct sh5pci_softc *);
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static int sh5pci_interrupt(void *);
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/*
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* XXX: These should be allocated dynamically to allow multiple instances.
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@ -302,7 +303,8 @@ sh5pciattach(struct device *parent, struct device *self, void *args)
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*/
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sc->sc_intr = sh5pci_get_intr_hooks(&sh5pci_chipset_tag);
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sc->sc_intr_arg = (sc->sc_intr->ih_init)(&sh5pci_chipset_tag,
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NULL, NULL, NULL, NULL, NULL, NULL);
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&sc->sc_ih_serr, sh5pci_interrupt, sc,
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&sc->sc_ih_err, sh5pci_interrupt, sc);
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/*
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* Initialise the host-pci hardware
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@ -322,14 +324,23 @@ sh5pciattach(struct device *parent, struct device *self, void *args)
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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/*
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* Allocate some I/O space for the bridge's config registers
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* before assigning addresses to any other device.
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* (The bridge doesn't seem to be able to see its own config
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* registers when doing config cycles. Let's hope they're
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* visible if the bridge is running in non-host mode...)
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* Reserve the lowest 256 bytes of i/o space. Some (older) PCI
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* devices don't like to be assigned such low addresses...
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*/
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extent_alloc(ioext, 0x100, 0x100, 0, EX_NOWAIT, &cfg_ioaddr);
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sh5pci_csr_write(sc, SH5PCI_CONF_IOBAR, cfg_ioaddr|PCI_MAPREG_TYPE_IO);
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/*
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* The SH5 Host-PCI bridge appears to be unable to see its own
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* configuration registers in PCI config space, so manually fix
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* up some values.
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*/
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sh5pci_csr_write(sc, SH5PCI_CONF_IOBAR, 0x40000);
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{
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u_int32_t reg;
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reg = sh5pci_csr_read(sc, PCI_BHLC_REG);
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reg |= (0x80 << PCI_LATTIMER_SHIFT);
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sh5pci_csr_write(sc, PCI_BHLC_REG, reg);
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}
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/*
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* Configure up the PCI bus
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@ -347,7 +358,8 @@ sh5pciattach(struct device *parent, struct device *self, void *args)
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pba.pba_pc = &sh5pci_chipset_tag;
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pba.pba_bus = 0;
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pba.pba_bridgetag = NULL;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
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PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
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pba.pba_dmat = &sh5pci_dma_tag;
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pba.pba_iot = &sh5pci_io_tag;
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pba.pba_memt = &sh5pci_mem_tag;
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@ -845,6 +857,12 @@ sh5pci_bridge_init(struct sh5pci_softc *sc)
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u_int32_t reg;
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int i;
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/* Disable the bridge */
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reg = sh5pci_csr_read(sc, SH5PCI_CSR_CR);
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reg &= ~SH5PCI_CSR_CR_PCI_CFINT_WR(1);
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reg |= SH5PCI_CSR_CR_PCI_CFINT_WR(0);
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sh5pci_csr_write(sc, SH5PCI_CSR_CR, reg);
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/*
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* Disable snoop
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*/
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@ -860,28 +878,29 @@ sh5pci_bridge_init(struct sh5pci_softc *sc)
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sh5pci_csr_write(sc, SH5PCI_CSR_AINTM, 0);
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sh5pci_csr_write(sc, SH5PCI_CSR_PINTM, 0);
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/*
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* Now enable the bridge.
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*/
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reg = sh5pci_csr_read(sc, SH5PCI_CSR_CR);
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reg |= SH5PCI_CSR_CR_PCI_FTO_WR(1); /* TRDY and IRDY Enable */
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reg |= SH5PCI_CSR_CR_PCI_PFE_WR(1); /* Pre-fetch Enable */
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reg |= SH5PCI_CSR_CR_PCI_BMAM_WR(1); /* Round-robin arbitration */
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reg |= SH5PCI_CSR_CR_PCI_PFCS(1); /* 32-bytes prefetching */
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sh5pci_csr_write(sc, SH5PCI_CSR_CR, reg);
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reg |= SH5PCI_CSR_CR_PCI_CFINT_WR(1); /* Take bridge out of reset */
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sh5pci_csr_write(sc, SH5PCI_CSR_CR, reg);
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/*
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* Enable Memory and I/O spaces, and enable the bridge to
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* be a bus master.
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*/
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reg = sh5pci_csr_read(sc, PCI_COMMAND_STATUS_REG);
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reg &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT);
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reg &= ~(PCI_COMMAND_MASK << PCI_COMMAND_SHIFT);
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reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE) << PCI_COMMAND_SHIFT;
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PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_STEPPING_ENABLE)
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<< PCI_COMMAND_SHIFT;
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sh5pci_csr_write(sc, PCI_COMMAND_STATUS_REG, reg);
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/*
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* Now enable the bridge.
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*/
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reg = SH5PCI_CSR_CR_PCI_FTO_WR(1); /* TRDY and IRDY Enable */
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reg |= SH5PCI_CSR_CR_PCI_PFE_WR(1); /* Pre-fetch Enable */
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reg |= SH5PCI_CSR_CR_PCI_BMAM_WR(1); /* Round-robin arbitration */
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reg |= SH5PCI_CSR_CR_PCI_HOSTNS(1);
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reg |= SH5PCI_CSR_CR_PCI_CLKENS(1);
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sh5pci_csr_write(sc, SH5PCI_CSR_CR, reg);
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reg |= SH5PCI_CSR_CR_PCI_CFINT_WR(1); /* Take bridge out of reset */
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sh5pci_csr_write(sc, SH5PCI_CSR_CR, reg);
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/*
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* Specify the base addresses in PCI memory and I/O space to
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* which SuperHyway accesses are mapped.
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@ -897,7 +916,7 @@ sh5pci_bridge_init(struct sh5pci_softc *sc)
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sh5pci_csr_write(sc, SH5PCI_CSR_MBR, (~SH5PCI_MEMORY_SIZE) + 1);
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sh5pci_csr_write(sc, SH5PCI_CSR_IOBMR,
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SH5PCI_CSR_IOBMR_PCI_IOBAMR(SH5PCI_MB2IOBAMR(8)));
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SH5PCI_CSR_IOBMR_PCI_IOBAMR(SH5PCI_KB2IOBAMR(256)));
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sh5pci_csr_write(sc, SH5PCI_CSR_IOBR, 0);
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/*
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@ -911,7 +930,7 @@ sh5pci_bridge_init(struct sh5pci_softc *sc)
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SH5PCI_CSR_LSR_PCI_MBARE);
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sh5pci_csr_write(sc, SH5PCI_CSR_LAR(0), SH5PCI_RAM_PHYS_BASE);
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sh5pci_csr_write(sc, SH5PCI_CONF_MBAR(0),
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0x00000000 | PCI_MAPREG_TYPE_MEM |
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0x80000000 | PCI_MAPREG_TYPE_MEM |
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PCI_MAPREG_MEM_TYPE_32BIT | PCI_MAPREG_MEM_PREFETCHABLE_MASK);
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sh5pci_csr_write(sc, SH5PCI_CSR_LSR(1),
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@ -920,7 +939,7 @@ sh5pci_bridge_init(struct sh5pci_softc *sc)
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sh5pci_csr_write(sc, SH5PCI_CSR_LAR(1),
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SH5PCI_RAM_PHYS_BASE + 0x20000000);
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sh5pci_csr_write(sc, SH5PCI_CONF_MBAR(1),
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0x20000000 | PCI_MAPREG_TYPE_MEM |
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0xa0000000 | PCI_MAPREG_TYPE_MEM |
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PCI_MAPREG_MEM_TYPE_32BIT | PCI_MAPREG_MEM_PREFETCHABLE_MASK);
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/*
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@ -940,15 +959,11 @@ sh5pci_bridge_init(struct sh5pci_softc *sc)
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sc->sc_map[i].m_start = ~0;
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}
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#if 0
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/*
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* XXX: Not yet
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*
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* Enable interrupts
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* Enable PCI error/arbiter interrupts
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*/
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sh5pci_csr_write(sc, SH5PCI_CSR_INTM, 0);
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sh5pci_csr_write(sc, SH5PCI_CSR_AINTM, 0);
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#endif
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sh5pci_csr_write(sc, SH5PCI_CSR_INTM, ~0);
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sh5pci_csr_write(sc, SH5PCI_CSR_AINTM, ~0);
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}
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static int
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@ -970,3 +985,30 @@ sh5pci_check_master_abort(struct sh5pci_softc *sc)
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return (rv);
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}
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static int
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sh5pci_interrupt(void *arg)
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{
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struct sh5pci_softc *sc = arg;
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u_int32_t pci_int, pci_air, pci_cir;
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pci_int = sh5pci_csr_read(sc, SH5PCI_CSR_INT);
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pci_cir = sh5pci_csr_read(sc, SH5PCI_CSR_CIR);
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pci_air = sh5pci_csr_read(sc, SH5PCI_CSR_AIR);
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if (pci_int) {
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printf("%s: PCI IRQ: INT 0x%x, CIR 0x%x, AIR 0x%x\n",
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sc->sc_dev.dv_xname, pci_int, pci_cir, pci_air);
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sh5pci_csr_write(sc, SH5PCI_CSR_INT, pci_int);
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}
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pci_int = sh5pci_csr_read(sc, SH5PCI_CSR_AINT);
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if (pci_int) {
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printf("%s: PCI Arbiter IRQ: AINT 0x%x, CIR 0x%x, AIR 0x%x\n",
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sc->sc_dev.dv_xname, pci_int, pci_cir, pci_air);
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sh5pci_csr_write(sc, SH5PCI_CSR_AINT, pci_int);
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}
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return (1);
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}
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