Remove the cache flush routines that have been moved to cpu.c
Make sure we clear out the unused PA bits in the TTE which causes breakage
on some MMU models.
sizes and line sizes. This is needed for cache flusing, clearing
memory, and several other operations. This information is accessible
from userland through a new CPU_CACHEINFO sysctl.
Audio-related stuff is left almost intact.
* support audiocs at ebus playback and capture
tested on krups and u5 (thanks, martin)
* make first attempt at supporting audiocs at sbus capture
* nb: full-duplex is not tested
* while here, fix CSAUDIO_MONITOR_MUTE to be of CSAUDIO_MONITOR_CLASS
i.e. outputs.monitor.mute -> monitor.monitor.mute
Ok by pk, eeh.
the others. It is perfectly reasonable to have multiple adb keyboards,
and a number of multi-button mice have a fake kbd for the second and
third mouse buttons. Now my machine doesn't panic during boot when it
is trying to add a second ws console kbd.
* Use BUS_ADDR() where appropriate to encode I/O space and physical
address offset into a `bus_addr_t' value.
* Drop obio_bus_map() since it's now completely equivalent to bus_space_map()
* Use bus_space_map2() to map device space at a fixed virtual address.
* Remove the virtual address argument from sbus_sbus_addr()
but not used resulting in a compiler error. By splitting the declaration
and the initialisation this is solved.
Better would be to not even declare the flag when ARMFPE isnt enabled but
that would just add to the #ifdef jungle.
- Reinstall the "dynamic page table length" that was removed some
years ago.
- Limit the user page table submap to max 5% of available memory.
- Free the page table space when a process is swapped out.
- If the UPT submap runs out of space, throw away pmap mappings
using the same algorithm as for swapping processes.
As a result of this, 4MB machines are useable again and it's even possible
to compile a kernel for 2MB machines (but it will be slow... :-)
Still to do:
- Multiprocessor fixes.
- More profiling.
tell nothing in the acorn32 port was using this version of
MEMORY_DISK_SIZE but I've left the code here incase the portmaster
wants it.
* rename MINIROOTSIZE to MEMORY_DISK_SIZE, so that all md(4) options
are consistently named
* fold opt_mdsize.h into opt_md.h
even bother probing for an FPA. If ARMFPE is configured, always use it,
even if there's an FPA (since it provides the FPA support code). Move all
printfs about FPAs into armfpe_init.c.
This means I can delete the last two elements from struct _cpu, so that the
structure, and the whole of <arm/cpus.h> is redundant and can be deleted.
This has been on my TODO list for some time and i found it time to fix it
since its pretty simple to do.
The patch checks if the kernel is booted from the `UnixFS' RISC OS filing
system (case unimportant) and if so interprets its name to get the unix
file name the kernel has. If it doesn't see this prefix it will asume its
just called `netbsd'
in identify_arm_cpu(), since it's almost unused elsewhere.
Change the detection of bugged StrongARMs to use the cpu ID rather than the
class. This turns "almost" into "entirely".
struct cpu_info. Also kill the cpuctrl global while we're here, and make
identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU
number.
deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map). Try to deal with this:
* Group all information about the backend allocator for a pool in a
separate structure. The pool references this structure, rather than
the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
to become available, but will still fail if it cannot callocate KVA
space for the pages. If this happens, carefully drain all pools using
the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
some pages, and use that information to make draining easier and more
efficient.
* Get rid of PR_URGENT. There was only one use of it, and it could be
dealt with by the caller.
From art@openbsd.org.
MIPS32 4Kc CPU board, with support for the MIPS64 5Kc and the QED RM5261
CPU boards to follow.
The cs4281 audio hasn't been tested, there are some interrupt problems
with onboard the pciide, but all other on-board peripherals work.
The evbmips port will support more MIPS evaluation boards in the future.
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
To implement a more accurate microtime using the CP0 COUNT
register we need to divide that register by the number of
cycles per MHz. But...
DIV and DIVU are expensive on MIPS (eg 75 clocks on the
R4000). MULT and MULTU are only 12 clocks on the same CPU.
On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
clocks for MUL/MULTU.
The strategy we use to to calculate the reciprical of cycles
per MHz, scaled by 1<<32. Then we can simply issue a MULTU
and pluck of the HI register and have the results of the
division.
"swarm"). Other SB-cpu boards will be supported by this port in
the future.
Includes support for on-chip ethernet and serial. Many features
still missing - notably SMP, PCI/LDT and IDE.
This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
and support routines for the Broadcom CFE (Common Firmware Environment).
This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
- Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
- Use a table-driven CPU detection algorithm instead of multiple
case statements.
- Add MIPS32/64 feature detection using the architected CP0 registers
(from Broadcom Corp).
- Call MD mips_machdep_cache_config() function if
__HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
L2 cache on some ports.
- Remove all mmu-related code that may use 32 register on mips32-style
implementatios and move them to mipsX_subr.S - which is then included
from mips{3,32,64,5900}_subr.S with various control defines enabled.
- Remove local cache instruction flags
- Add badaddr64 (from Broadcom Corp).
- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.
- Add XKPHYS macros (from Broadcom Corp).
- Add some r5900 register bit definitions.
- Add extra exception vector addresses for mips32/mips64 and r5900.
- Make the mips cp0 register definitions available from both asm and C.
- Add some Alchemy and Sandcraft CPU ids.
- Add r3000, tx39xx and r4x00 CPU revision ids.
- Remove defines for the number of TLBs on some CPUs.
eeh