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805 Commits

Author SHA1 Message Date
shin
e2711a6552 make it compile with -DDEBUG. 2000-04-21 14:10:39 +00:00
nisimura
79733cb614 Effort to have consistent comments, fixing one error. 2000-04-21 02:45:01 +00:00
nisimura
3d5a5b03f5 - Address PR#9907. u_pte[1] wired down is left not global sometimes. 
The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
  value for TLB invalidation routines.
 2000-04-21 02:39:55 +00:00
nisimura
a01973aecb Change the way how pmap_protect() modifies the protection of KSEG2 
space using MIPS_TBRPL() call.  It avoils to 'vistimize' a possibly
useful TLB entry. XXX MachTLBUpdate() will be retired, soon.
 2000-04-16 10:16:19 +00:00
nisimura
8feff14832 Fix a typo in the previous change. 2000-04-16 10:08:32 +00:00
nisimura
4edcc4fca2 Change the way to implement zero copy data move in pagemove() using 
MIPS_TBRPL().  It saves about 20 instructions to run for each
iteration, and avoids TLB polution.  Currently works for MIPS1 only
configuration.
 2000-04-16 09:09:42 +00:00
nisimura
7717409808 Introduce MIPS_TBRPL() which replaces a TLB entry of given vaddr 
with new entryHi and entryLo pair iff found in TLB.  Works only
for KSEG2 this moment.  mips3 version will follow.
 2000-04-16 09:00:26 +00:00
soda
c56a43535d remove following symbols which became unnecessary in recent cpu_intr() change: 
mips_hardware_intr
	MIPS3_INTERNAL_TIMER_INTERRUPT
	mips3_intr_cycle_count
	mips3_timer_delta
 2000-04-15 22:05:51 +00:00
nisimura
e54e10f9ce - Withdraw dealfpu() code which has been never useful so far. 
- XXX It was a mistake to add CP1 insn encoding values into cpuregs.h.
  Those will be relocated into mips_opcode.h with some adjustment work.
 2000-04-15 06:21:01 +00:00
soren
0ce39b7430 Typo; user stack only needs to start one page below 0x80000000. 2000-04-13 22:02:54 +00:00
nisimura
ce0937324b - Move a loop invariant of 'if (CPUISMIPS3)' out of pagemove(). 
- XXX I'm not sure whether the anticipatory MachTLBUpdate(to, pte) is
  a gain or loss on runtime.  If not a loss, it should be MIPS_TBIS().
 2000-04-12 01:37:58 +00:00
nisimura
85f3855a8c - Implement mips3_TBIAP(). 
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.
 2000-04-12 01:05:34 +00:00
castor
4ebaf4d105 Taken from Jeff Smith <jeffs@geocast.com>: 
Fix regress/lib/libc/ieeefp/except for MIPS.  Newer FPE handling code
	did not generate SIGFPE, but always SIGILL.  Add this back to the
	assembly code.  The QED 5231 requests the kernel emulates some of
	the conditions that generate an SIGFPE, but when the emulation code
	did a ctc1 to fsr with an exception the kernel got a FPE in kernel mode.
	Fix this by saving the fp regs earlier, then saving the new FSR in
	the context.  This allows the FSR value to be seen by the SIGFPE
	handler.

	Add fp emulation for 8 mips2 fpu instructions to handle exceptions
	(round.w.fmt, trunc.w.fmt, ceil.w.fmt, floor.w.fmt).  This lets
	perl5 run when compiled -mips2.
 2000-04-11 16:28:05 +00:00
nisimura
aa4f967e51 Abandon rather random distinctions in andi/addiu coding and make 
them consistent with and/addu instrunction mnemonics which produce
exactly same binaries.
 2000-04-11 04:53:57 +00:00
nisimura
dba7b560cd Load delay slot is automagically adjusted at runtime since MIPS II 
architecture.
 2000-04-11 04:39:14 +00:00
chs
a6d33cc1f2 add a new function vn_marktext() for exec code to let others know 
that the vnode is now being used as process text.
 2000-04-11 04:37:47 +00:00
nisimura
e342080364 Introduce cpu_intr() whose body is now provided by target ports in 
their own ways.  Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.
 2000-04-11 02:30:14 +00:00
nisimura
4f3093c121 Remove various TLB manipulation routines which have been unused 
long time, commented out and is unlikely useful; TLBWriteIndexed(),
TLBWriteRandom(), TLBFlush(), TLBFlushPID() and TLBFind().
 2000-04-11 01:32:19 +00:00
nisimura
53e7a8c8d5 - Fix a bug in mips1_TBIAP() misbehaving like as mips1_TBIA(). 
- Adjust comments to reflect what it does.
 2000-04-10 11:38:16 +00:00
simonb
3d6b29f228 Use UVM_PGA_ZERO in uvm_pagealloc() calls instead of using pmap_zero_page(). 2000-04-10 08:50:20 +00:00
nisimura
ea23dc6364 Make sure ASID management is done in the same way of NetBSD/alpha. Rename 
and change 'pmap_alloc_asid()' into 'pmap_asid_alloc()'
 2000-04-10 05:34:27 +00:00
nisimura
c84ed44f75 Make (sure) ASID management same as what NetBSD/alpha does for ASN. 
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID.   MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump.  Change for MIPS3 is
to be done.
 2000-04-10 04:59:46 +00:00
simonb
e2b66b68da Small white space and 80col wraparound cleanups. 2000-04-10 01:53:11 +00:00
soren
09ad839ab3 This file has been superseded by the MI ELF code. 2000-04-08 22:30:26 +00:00
soren
aa4c70110e Move the start of the user stack down a little to account for the 
virtual address checking done by the R8000 and some QED CPUs.

From Jeff Smith.
 2000-04-07 21:50:08 +00:00
simonb
9edec906b5 Removing trailing comma from enum declaration. 2000-04-03 05:58:31 +00:00
thorpej
2bc5adb20e Instead of checking vm_physmem[<physseg>].pgs to determine if 
uvm_page_init() has completed, add a boolean uvm.page_init_done,
and test against that.  Use this same boolean (rather than
pmap_initialized) in pmap_growkernel() to determine if we are
being called via uvm_page_init() to grow the kernel address space.

This fixes a problem on some i386 configurations where pmap_init()
itself was needing to have the kernel page table grown, and since
pmap_initialized was not yet set to TRUE, pmap_growkernel() was
choosing the wrong code path.

Fix tested by Havard Eidnes.
 2000-04-02 20:39:14 +00:00
minoura
78b105698a Move dl* function definitions to libc on ELF. 
Based on the patch supplied by Takuya Shiozaki <tshiozak@astec.co.jp>.
See http://mail-index.netbsd.org/tech-userlevel/2000/02/23/0000.html.
 2000-04-02 15:35:47 +00:00
simonb
6e0357239a Nuke register, diddle a bit of indentation in some function declarations. 2000-03-30 14:36:30 +00:00
nisimura
1b0c1f4d0d Abandon the initial microscale optimization of pmap_alloc_asid(), 
leaving the second change intact.  It'd be rather less costly to
extend the case analysis.
 2000-03-28 05:58:33 +00:00
simonb
6060929e8e Move fpcurproc declaration to <mips/cpu.h>. 2000-03-28 03:11:26 +00:00
simonb
ef89d70178 Don't `extern' function declarations. While we're there, remove trailing 
blank lines and white space.
 2000-03-28 02:58:44 +00:00
simonb
ea6aa0dc3c Use the recent alpha solution to getting the printf() format right in 
mips_init_msgbuf().
 2000-03-28 02:53:18 +00:00
simonb
338105f94b Make declaration of curpcb variable extern. 2000-03-28 01:06:04 +00:00
simonb
a833cd73e8 Remove duplicate declaration of pmap_is_page_ro() (in <mips/pte.h> and 
pmap_zero_page() (in <vm/pmap.h>).
 2000-03-28 01:04:22 +00:00
nisimura
464669d1ef The previous microscale optimazation in pmap_asid_alloc() was 
half-baked and resulted in one superfluous ASID bump if new pmaps
are created when pmap_asid_generation > 0.   Need to initialize pmap
fields correctly.

Yet, this possibly might not be the perfect solution.  If one
process bumped pmap_asid_generation _after_ a new pmap was created
and initialized with then-current pmap_asid_generation value.  In
that case, the new pmap would have another (superfluous) ASID bump
when 2nd (not 1st) CPU tick is assigned.  I'm not sure if this case
would happen.

Have pmap_max_asid variable to hold the maximum number of ASID
(TLBpid) supported by processor anticipating the possible runtime
cost of ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS).
 2000-03-28 01:00:00 +00:00
simonb
8ae7eeef11 Remove redundant declarations of mips3_cycle_count(), stacktrace(), 
logstacktrace(), mips_idle() and cpu_switch() - these are already
declared in various header files.
 2000-03-28 00:55:33 +00:00
simonb
d0e1814cba Remove duplication declarations of Sysmap and Sysmapsize - these are 
in <mips/pte.h>
 2000-03-28 00:52:57 +00:00
nisimura
73fa1ce87f Change 'goto cpu_switch1' to 'goto cpu_switch_queuescan' in vr_idle.S 
and make the jump destination global.
 2000-03-28 00:24:04 +00:00
nisimura
fa6012454d It's not necessary to (re-) assign pmap->pm_asidgen whenever ASID 
(TLBpid) is bumped.  It's ok just in the case when pmap_asid_generation
is bumped.
 2000-03-27 08:56:21 +00:00
nisimura
06b4feb7d6 Have TBIA/TBIAP an argument refering to a global variable instead 
of a compile time constant.
 2000-03-27 05:30:40 +00:00
nisimura
5987070300 - Rename some of TLB ops to have handy abbrivations hired from VAX and 
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
  which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

- XXX XXX XXX
  it's less-than-optimal and likely a mistake to have TLBUpdate().
  It's costy to try to invalidate a single TLB entry whenver a certain
  PTE is going to be modified by traversing the entire TLB looking
  for the modified PTE because the PTE in question is not in TLB in
  most cases.  ASID bump could do the invalidation smartly.  Solution
  is planned for now.
 2000-03-27 05:23:42 +00:00
nisimura
cbab853044 Rename sw1 label found in cpu_switch() to cpu_switch_queuescan, 
abandoning unnecessary .globl because switch_exit() is handsomely
common between MIPS1 and MIPS3.
 2000-03-27 04:52:11 +00:00
nisimura
24571569fa Nuke MIPS_16K_PAGE conditional which should be commited in. It 
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.
 2000-03-27 02:55:13 +00:00
kleink
230876cf26 Merge parts of chs-ubc2 into the trunk: 
* Remove the casts to vaddr_t from the round_page() and trunc_page() macros to
  make them type-generic, which is necessary i.e. to operate on file offsets
  without truncating them.
* In due course, cast pointer arguments to these macros to an appropriate
  integral type (paddr_t, vaddr_t).

Originally done by Chuck Silvers, updated by myself.
 2000-03-26 20:42:21 +00:00
nisimura
b6b06284ce Add QED RM7000 PrID. 2000-03-25 06:33:50 +00:00
soren
573160e03b Revert previous. 2000-03-24 23:06:03 +00:00
soren
c535ede30b Move sysctl definitions from arch/mips to arch/foo. 2000-03-24 21:30:58 +00:00
soren
a0c624dd3d Remove FPU PRIDs that are identical to the CPU ones. 2000-03-24 20:48:20 +00:00
soren
059fe2fbb2 One instruction per line. 2000-03-24 18:16:33 +00:00
soren
2531a231d2 Missing in previous; set cache alias mask properly on processors with 
two-way set associative L1 caches.
 2000-03-24 18:15:41 +00:00
nisimura
3af954d380 Have ST_REG_SR mnemonic for status register consistent with others. 2000-03-24 02:02:03 +00:00
soren
1c965174b0 Make MIPS1+MIPS3 compile again. 2000-03-23 14:49:29 +00:00
soren
64bcb49a2e Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast. 
Many thanks.
 2000-03-19 19:16:13 +00:00
tron
e86957458a Install "machineendian_machdep.h". 2000-03-17 22:36:31 +00:00
mycroft
9e21b6555a In the `MY THAT'S GROSS' department... 
Eliminate the recursive include of machine/endian.h from sys/endian.h.
 2000-03-17 00:09:18 +00:00
mycroft
02905321b2 Foolish consistency. Mainly, always use underscores and sys/endian.h. 2000-03-16 15:09:34 +00:00
soren
667929def5 KNF comment. 2000-03-14 14:11:06 +00:00
soren
9ec86df3dd Fix typo. 2000-03-14 14:10:08 +00:00
soren
eb9d73ce81 Actually use KSEG1 offset for KSEG1 addresses in kvtophys(). 
From Jeff Smith and Ethan Solomita at Geocast.
 2000-03-14 14:08:55 +00:00
kleink
0c7df56c40 Define ISO C99 (unsigned) long long (min, max) symbols. 
VS: ----------------------------------------------------------------------
 2000-03-07 19:31:50 +00:00
soren
2f1aff2da3 Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions. 2000-03-07 01:05:48 +00:00
nisimura
03bf9a2dc3 Remove #ifdef'ed out PMAX_CACHEFLUSH_FORCES_WBFLUSH codes in cache 
flush ops which has had no effect for long time.
 2000-03-04 11:37:31 +00:00
soda
c616c9e0fe use callback function to set up secondary cache related things on arc. 
XXX - perhaps it is better to separate cache related initialization
from mips_vector_init().
 2000-03-03 12:43:52 +00:00
castor
67e96268ad Fix a /dev/kmem crash when vaddr + count wrapped and snuck through 
the error check, courtesy of Jeff Smith <jeffs@geocast.com>.
 2000-03-03 02:33:21 +00:00
mhitch
e48c624741 Loading the exception return PC in k0 before restoring the status register 
(which disables the interrupts) is *not* a good idea.  k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.
 2000-02-23 17:04:06 +00:00
soda
6ff57360cc mips is now vm_offset_t/vm_size_t clean 2000-02-22 12:28:25 +00:00
erh
8f03b9a04a Define the DONETISR macro and use netisr_dispatch.h. This is to cut down on code duplication and to standardize the available NETISRs across all ports. 2000-02-21 20:38:46 +00:00
mycroft
7f0554e0c9 Add some CONSTCONDs to make lint happier. 2000-02-19 09:23:44 +00:00
mycroft
09cc3151e6 Don't pull in cpu.h in non-kernel code. 2000-02-19 09:22:51 +00:00
mycroft
6fe5b35136 Don't print an extra cpu0: prefix. 2000-02-19 04:00:59 +00:00
mycroft
b4f04eeaad Disable the sN,sp,gp register restore code for now, as it seems to collide with 
something else.
 2000-02-19 01:56:21 +00:00
thorpej
bb7c9c63f3 On exception return, use k1 to restore the saved registers, so that we 
don't stomp on the return address in k0.  Also, don't need to account
for any load delays, as the last register restored (gp) isn't used in
the subsequent instruction.
 2000-02-18 18:36:41 +00:00
mycroft
c9f3b6ba01 Adjust previous change for R3000 load delay slot. 2000-02-18 03:46:43 +00:00
mycroft
71979ea6fb Make the MIPS1 and MIPS3 code more similar. 
XXX Needs testing on MIPS1.
 2000-02-18 00:15:15 +00:00
mycroft
9e77fba716 Take a whack at allowing sN, sp and gp to be set from DDB, too. 2000-02-18 00:02:43 +00:00
mycroft
3ade108e4b Allow vN, aN, tN, ra, sr, mul[lo,hi] and pc to be set from DDB. sN requires 
more work.
 2000-02-17 23:52:23 +00:00
thorpej
fd8c03cf44 Allow arch-specific code to specify in4_cksum() like it can specify 
in_cksum().
 2000-02-14 21:42:50 +00:00
thorpej
dded044fc2 Update for the NKMEMPAGES changes. 2000-02-11 19:25:12 +00:00
shin
7f5a7c00ac fix include file. 
<netinet6/ip6.h>	->	<netinet/ip6.h>
 2000-02-09 05:48:26 +00:00
kleink
36e6bc645e Improve namespace test macros a bit. 2000-02-05 14:04:36 +00:00
kleink
82464e46d6 Add a C99-style va_copy macro. 2000-02-03 16:16:06 +00:00
thorpej
474894e5f6 Fix a bug in cpu_switch() introduced with the MIPSX_CPU_IDLE changes; we 
have a 1 instruction delay after a load before the register contents are
valid on the R2000/R3000.
 2000-02-01 18:49:03 +00:00
thorpej
1247bea5c2 No need for mips_locore_jumpvec to be initialized data. 2000-02-01 18:38:50 +00:00
takemura
39bbf02101 Delete unused lines. 2000-01-28 15:18:32 +00:00
takemura
ae6160e233 CPU specific idle hook and VR idle routine. 2000-01-28 15:08:36 +00:00
soren
a5cef94d04 We don't really have 'mach trapdump'. 2000-01-26 13:36:05 +00:00
tsutsui
b0fbaa33fb Remove obsoleted macros. 2000-01-26 09:44:10 +00:00
sommerfeld
aa195e816f Fix PR9240: comment above cpu_fork() out of synch with reality on most ports. 
(comment change only, but was wrong for more than just i386).
 2000-01-20 22:18:54 +00:00
thorpej
a0397a2573 Move callout initialization to a single location; no need to duplicate 
that code all over the place.
 2000-01-19 20:05:30 +00:00
simonb
b4c00759ec Clear up a comment a little. 2000-01-09 20:08:14 +00:00
simonb
24ddcc3162 Use the badaddr() prototype in mips/include/cpu.h by including 
<machine/cpu.h> in mips/include/mips_param.h.  Remove duplicate
badaddr() prototypes from some pmax header files.
 2000-01-09 13:24:14 +00:00
simonb
ddc897f64e Prototype stacktrace() and logstacktrace(). 2000-01-09 10:05:55 +00:00
shin
5a5de631b0 split 'options SOFTFLOAT' to 
NOFP		don't touch FPU registers in kernel
	SOFTFLOAT	emulate FPU instructions in kernel
 2000-01-09 08:01:54 +00:00
kleink
693059feda const -> __const and include <sys/cdefs.h> earlier; fixes PR lib/9052 
by Takahiro Kambe.
 2000-01-04 14:20:05 +00:00
castor
7fc2807b2b Make SOFTFLOAT emulation compatible with _MIPS_BSD_API_LP32_64CLEAN 1999-12-29 04:41:12 +00:00
castor
2a0deb6e74 Add code to ensure delay slot is printed when disassembling. 1999-12-27 21:12:25 +00:00
castor
cf643fe983 Add macro for MIPS_PHYS_MASK and document use of bits in system status 
registers.
 1999-12-27 20:05:06 +00:00
kleink
11e6c54cfc C99: Define a NAN macro in <math.h> which evaulates to a constant expression of 
a single-precision quiet NaN; only to be defined on platforms that do support
this value.
 1999-12-23 10:15:05 +00:00
tsubai
ea69e534d2 * news5000 support. 
* mips3_VCE[DI] now support L2CacheLSize != 32.
 1999-12-22 05:54:18 +00:00