Commit Graph

415 Commits

Author SHA1 Message Date
thorpej 631447bb4a Change some #if 0 to #ifdef VERBOSE_INIT_ARM. 2001-12-18 02:52:00 +00:00
bjh21 f2ebadcc6f Ensure that vidc.h gets installed somewhere -- Xarm32vidc needs it to compile. 2001-12-17 15:07:37 +00:00
bjh21 7bc474a92b mod() was unused. g/c it. New code should use abs() anyway. 2001-12-15 22:41:44 +00:00
bjh21 eefdf030c9 Simplify the pixel-clock-rate-setting code, so it always works out the
parameters from first principles rather than using a static table for some
rates.  This makes it work correctly on ARM7500, for which the table was
bogus (ARM7500 has a different refclk from VIDC20).
2001-12-15 22:21:46 +00:00
chris 80e667c6ab Add clockctl device.
Note that someone needs to tidy this up, we've got 92 block devices, which just ain't true.  Also appears we're actually missing some, eg the ld block device.
2001-12-11 00:34:50 +00:00
thorpej 51535d4bf5 Add support for dumping ELF-cormat core files. 2001-12-09 23:05:56 +00:00
atatat b45c51b1fc Roll the rest of the ports over to the new MI kernel build machinery.
Any problems reported by testers have been fixed, and massive
cross-compiling of kernels has shown that any problems that remain
with actually building kernels are not related to this.
2001-12-09 05:00:40 +00:00
chris 3831bfec98 Improve comment on the clockswitching asm code, it doesn't use r0 at all, it just needs it to make valid asm. 2001-12-08 21:30:04 +00:00
chris ce689bde4d Fix the asm macros
The tmpx registers are now outputs, this makes them all unique.
Add the fact that cc is changed by the asm (not believed to be used but rather be correct)
Correctly specify w as an input and output register, I think this was hiding the bug below!
Allow sum to be in a different input and output register.

Correct bug in psuedo header handling for in4_cksum.  Seems that the new macros turned up a latent bug in the psuedo header handling, the code was moving a pointer forward 16 bytes twice, not found before as the ADD16 macro wasn't 100% accurate, as it didn't output w, even though it modified it.
2001-12-08 21:18:50 +00:00
thorpej 72dee19a8c Reset the i80200 ICU and PMU to a pristine state very early. 2001-12-01 23:06:45 +00:00
bjh21 e4dac015cd Don't define get_cachetype() unless it's going to be used. 2001-12-01 14:21:18 +00:00
thorpej 3fd0a58e9d On the i80200, disable ECC in the Bus Controller Unit early on; we
don't really have code to deal with ECC errors yet.
2001-12-01 06:33:40 +00:00
thorpej 5936a89bf5 Add register definitions for the i80200 Interrupt Controller Unit,
Bus Controller Unit, and Performance Monitoring Unit.
2001-12-01 05:46:19 +00:00
thorpej 2b08dcc43b Clarify a comment to state that it is intentional that we attach
only the Secondary PCI bus (it's the only bus which can have a
device space hidden from any PCI host on the Primary bus).

Also, use the bus number from the PPB businfo register seecondary bus
field rather than hard-coding "1".
2001-11-30 19:29:44 +00:00
thorpej e90eccc52c Clarify a comment. 2001-11-30 19:26:03 +00:00
thorpej a2c8fc94fe Provide a way for platforms to move away from the old RiscPC-centric
interrupt code.  Garbage-collect some unused stuff.
2001-11-29 17:14:02 +00:00
thorpej a93f7ef419 Provide a hook for platform-specific interrupt code to specify
the "spl" cookie in the switch frame.
2001-11-29 17:12:22 +00:00
thorpej b0f775a467 Remove some overly-paranoid debug code that grovels too much
platform-specific internals.
2001-11-29 17:10:31 +00:00
thorpej 8ae5055ed9 Add routines for accessing the general purpose I/O facility of
the i80312 Companion I/O chip.
2001-11-29 08:27:11 +00:00
thorpej 574dba96b1 Update copyright. 2001-11-29 08:26:18 +00:00
thorpej c5ecb8d8c5 Use the new arm_dcache_align variable to set the PCI device BHLC
register.
2001-11-29 02:26:50 +00:00
thorpej 959181a8b2 Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors.  Report this when the processor is attached.
2001-11-29 02:24:58 +00:00
thorpej 636e9cd08b Add a "cacheline_size" argument to pci_configure_bus(). It is used
to set the cacheline size in the BHLC register.  This should be the
size of the largest D-cache line on a system.
2001-11-28 23:48:34 +00:00
thorpej 85a1db0fda Disable MRL, MRM, and MWI for now. 2001-11-28 22:39:09 +00:00
thorpej bd3e75a9df Oops, make sure to add in the physical base of the PCI memory
window when mapping PCI mem space.  (Whee, I can take out my
local hack, now).
2001-11-28 21:08:47 +00:00
lukem ecb81c3f6d - convert usage of "defopt" to "defflag" where the relevant option does
not support a value (e.g., it's to be used as "options FOO" instead of
  "options FOO=xxx"). options that take a value were converted to
  defparam recently.
- minor whitespace & formatting cleanups
2001-11-28 10:21:10 +00:00
thorpej 379948c31f - Garbage-collect some unused cruft.
- When processing ASTs, restore interrupts *after* clearing astpending.
2001-11-28 01:06:19 +00:00
thorpej b9caa4cbc7 Don't grovel interrupt-related info here; if a platform wants to
do that, let it do that in a way it can control.
2001-11-28 00:19:53 +00:00
thorpej a2fa0b1029 Add prototypes for new XScale write-through cache routines. 2001-11-28 00:18:46 +00:00
thorpej 8e96318c12 Don't define interrupt handler-related offsets here. 2001-11-28 00:18:13 +00:00
thorpej 28466919a2 Use <machine/intr.h> rather than <machine/irqhandler.h> 2001-11-27 01:03:52 +00:00
thorpej 8cd82ab7b7 Move interrupt-related stuff out of the generic 32-bit ARM genassym.cf
and into platform-specific genassym.cf files.
2001-11-27 00:15:58 +00:00
thorpej ed112809c9 Allow port-specific Makefile fragments to specify a list of additional
genassym.cf fragments, if desired.
2001-11-26 23:44:58 +00:00
thorpej 2d89f9075b Move interrupt-related stuff out of stubs.c into intr.c. 2001-11-26 23:19:04 +00:00
thorpej bb706190b3 Add code to run the XScale cache in write-though mode, and do so
for now...
2001-11-26 22:26:44 +00:00
thorpej 0ca43a5fde Use <arm/arm32/psl.h>, not <machine/psl.h>. 2001-11-26 20:51:57 +00:00
thorpej c8c624e4aa Don't include <machine/psl.h> directly. 2001-11-26 20:49:04 +00:00
thorpej 534b950d29 Move the interrupt-related file declarations into port-specific
config descriptions so that each port choose whether or not to
use it.
2001-11-26 20:33:43 +00:00
thorpej 8ec81cf263 Sprinkle CPWAIT around to enforce some barriers. Also deal with some
pre-B-step errata: must clean-dcache-line to an address before
invalidate-dcache-line to that address, or the dirty bits will not
get cleanred in the dcache array for that line.
2001-11-26 18:09:08 +00:00
thorpej 3b97bd4996 Remove dummy includes. 2001-11-26 01:03:58 +00:00
thorpej da03707c2f Moved to <sys/disklabel_acorn.h> 2001-11-26 01:03:23 +00:00
thorpej e4b45721eb Remove Shark-specific header file. 2001-11-26 01:03:00 +00:00
thorpej dc19fe137e Don't install includes which userland doesn't need. 2001-11-26 01:02:28 +00:00
thorpej 013b705fdc G/c the unused (and #if 0'd) bits of cpu_disklabel. Fetch disklabel_acorn.h
from the correct place.
2001-11-25 19:02:03 +00:00
thorpej 2b74082b7b End the "new ARM includes strategy" experiment. The new strategy
broke too many assumptions makde by other parts of the source tree,
and the strategy and how it was supposed to work was never discussed
on tech-userlevel, nor was it applied consistently (to all ARM ports
and to other ports which have common MACHINE_ARCH code, such as MIPS,
m68k, powerpc).

Verified to complete a full "make build" on cats, dnard, evbarm,
and netwinder.
2001-11-25 15:55:53 +00:00
thorpej c5269c1608 Make the ARM, Ltd. floating point emulator work w/ ELF. 2001-11-24 03:39:17 +00:00
thorpej 87fe867c21 Move the ARM, Ltd. floating point emulator to arch/arm. 2001-11-24 01:26:23 +00:00
thorpej fc019be5fd Use <arm/undefined.h> instead of <machine/undefined.h>. 2001-11-23 21:18:29 +00:00
thorpej 0c57d87232 Use <arm/cpufunc.h>, not <machine/cpufunc.h>. 2001-11-23 19:21:47 +00:00
thorpej d60ef922be Disable the BTB by default on the XScale again; there's some early
stepping errata to deal with before we can safely do this.
2001-11-23 19:17:04 +00:00