where the printing of `version' is already performed.
This has the benefit of allowing the copyright to be available
via dmesg(8) on platforms which need the `msgbuf' to be setup
in cpu_startup() before printed output is remembered.
distinction between signalling NaNs and quiet NaNs back into the
machine-dependent headers; treat the implementation of __nanf in the
same spirit.
IEEE 754 leaves the distinction between signalling NaNs and quiet NANs
to the implementation, and unlike our headers used to suggest they're
not identical in the interpretation of the fraction's MSb; in due
course, make those of hppa, mips, sh3, and sh5 reflect reality.
in inline asm and include turning the DMMU off and back on. This
prevents the compiler (especially gcc -O0) from inserting accesses to
locations in virtual address space when such accesses would fail.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.
(1) in pmap_enter_pv(), we would always mark the header entry wired, even if
the new entry wasn't put there. noticed by Juergen Hannken-Illjes.
(2) in pmap_unwire(), we would never examine the header entry.
noticed by me.
while I'm here, move the counter increment in the pmap_enter() path to be
next to the corresponding PV_WIRE() call so it's more obvious they match.
Rename consinit() to obs405_consinit() at evbppc/obs405/consinit.c.
Set md_consinit to obs405_consinit() at initppc().
Consinit fuction calls a function stored at md_consinit pointer.
Idle call that. Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.
- ibm40x_machdep.c: ibm40x specific
. ibm40x_memsize_init
. mem_regions
. other functions are moved to machdep.c or ibm4xx_machdep.c.
- ibm4xx_machdep.c: ibm4xx specific
. ibm4xx_init (moved from ibm40x_machdep.c)
. ibm4xx_install_extint (moved from ibm40x_machdep.c)
. ibm4xx_cpu_startup (moved from ibm40x_machdep.c:ibm4xx_startup)
. ibm4xx_dumpsys
- openbios.c
getting board data memory image from openbios.
setting all board data to board properties database.
- board_prop.c
initialize board properties database.
(set/get board properties [macros in ibm4xx/cpu.h])
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.
obtained.
Switch to EVCNT_ATTACH_STATIC*
In DEBUG/DIAGNOSTIC, decrement/increment pmap_pvo_enter_depth around pool
calls since they could possibly cause a recursion back into pmap_pvo_enter.
This areas is called the comm pages. It is used to provide fast access to
several data and functions.
The comm pages are mapped starting at 0xffff800 (address chosed so that
absolute branch can be used, so it can be accessed even when dynamic linking
is not ready). NetBSD has the user stack here, so we need to provide a
Darwin-specific stack setup routine which sets the top of the stack at
0xbfff0000.
This implementation is not complete but it does enough to get MacOS X.3
starting again (static binaries run, dynamic binaries still have an issue).
in the comm pages functions, we only implement bcopy, pthread_self and
memcpy.
TODO:
- clean up the powerpc specific code from MD parts
- for now we map only one page to avoid a crash, we want two pages.
- write all the comm functions.
we're executing on; besides dealing with the bits not implemented in the
601's MSR it also removes the silent failure behaviour when passing
PSL_VEC set on a CPU not implementing it.
Also, fix those masks for the 4xx again.
obliteration to RESTORE_{KERN,USER}_SRS, respectively; have oea_init()
patch these sequences to be skipped on non-MPC601s. The code sequence
matching heuristic isn't as pretty as the one for VRSAVE and MQ but works
well enough with the current structure of the trap code, and can be easily
updated when necessary.
Nuke struct fpu and use struct fpreg instead (except for the names, they
were identical). On MP machines, this will avoid an unneeded IPI to save
the register contents that are about to discarded.
Add a PSL_USEROK_P(psl) macro which valids the bits (replaces the use of
PSL_USERSTATIC).
Add a PSL_USERSRR1 mask which is used to mask out status bits in the upper
half of SRR1.
Make sure PSL_VEC is set appropriately in userret(). PSL_VEC is in the same
region as SSR1 status bits so it's not preserved on exceptions. Thus we
need to make to set it.
When returning a MSR/SRR1 to userland, always clear the status bits.
Add emulation of the mfpvr, mtmsr, and mfmsr instructions.
PSL_{FP|VEC} instead of PCB_{FP|VEC}. The former will only be set if the
process owned the {FP,VEC} unit when it trapped into the kernel. The latter
would be set if the lwp ever used the {FP,VEC} unit.
if the lwp doesn't currently own the FPU. When returning, copy those bits
back to the PCB. (In case the user decided to the FP exception mode in the
signal handler).
there, they will copied to MSR as needed (when FP is enabled). They will be
cleared from the MSR when the lwp loses the FPU. Hence they need to be stored
someplace else.
clear PSL_FP bit (to force a FPU Unavailable exception) but clear
PSL_FE0 and PSL_FE1 so that the FP execption mode is changes to ignore.
This will prevent spurious FP exceptions being made when the running lwp
doesn't own the FPU.
problems when we shift it left and right while creating the new value
for the condition register.
Fixes problems reported by Juergen Hannken-Illjes in toolchain/24938.
