a couple of typos so that it will work as I think that it was
intended to: delay for 10000us or 200us on transitions to/from D3
or D2 state, respectively. Discussed this with jmcneill@.
allocated by the AGP driver in the case of Intel chipset graphics.
This is different from the patch by Yorick Hardy circulated a while ago
in that it doesn't change the semantics of reference counting within
the (3rd-party) DRM code -- it just bypasses it.
Needless to say that it is uglier, but it eases future updates to
the DRM code because the change there is just 2 LOC.
Imo, a cleaner solution for all that would be to attach "agp" to "vga"
in the intel chipset graphics case, which better reflects how the hardware
is structured. This would still need a hack to the DRM code, but
it would be confined to childs of the "vga" device, without need for
global variables.
Since there is a variety of intel chipsets with AGP and/or builtin
graphics options, this would need a considerable testing effort.
-use an aligned pci config space address as everyone else -- I'm sorry
about that because I like gson's way a lot -- it keeps the address
offset due to alignment visually close to the data shift --, but since
aligned addresses are used everywhere else in definitions, this
causes confusion
-the mask applied to the data didn't make much sense, a look at the
FreeBSD code where this code originates from suggests that there
was just a mistake -- one trailing zero missing --
anyway, the datasheet tells that the error bits are all write-one-
to-clear, so just write back the value and we are done
are switched to (was harmless because we don't do D2 yet and also
don't (hmm - shouldn't) access devices in D3 (which would only make
sense if we'd support D3hot)
-zero the io/mem/master enable bits before entering D3
(The special handling of PCI_CLASS_DISPLAY devices is questionable
here -- we can't care about the console if we are seriously follow
the spec, and upstream bridges aren't considered anyway.)
-add exact references to the PCI PM spec
the opportunity to handle an ioctl before generic ifioctl handling
occurs. This will ease extending the kernel and sharing of code
between drivers.
First steps: Make the signature of ifioctl_common() match struct
ifinet->if_ioctl. Convert SIOCSIFCAP and SIOCSIFMTU to the new
ifioctl() regime, throughout the kernel.
establish the interrupt handler before enabling interrupts, so that
we will not get an interrupt storm that keeps the system from making
any progress. (We may have only been susceptible to the storm if
cbb(4) shared an interrupt with, say, uhci(4)). Also, finish
setting up the pcic_handle before enabling interrupts, so that the
Pcic_read() call in pccbbintr() will not jump to address 0!
Now, pccbb_intrinit() encapsulates all of the interrupt initialization.
Explicitly enable card-status changed (CSTSCHG) events.
Paranoia: ensure that writes to the socket event register (interrupt
acknowledgements) are flushed to the h/w by reading the register
(gross). We really need something like
bus_space_sync(BUS_SPACE_BARRIER_WRITE_BEFORE_INTERRUPT).
More paranoia: in pccbbintr(), if the device is inactive, get out.
Remove NetBSD 1.6 compatibility checks (way out of date).
Be somewhat consistent (and closer to KNF) with whitespace.
Use uintN_t instead of u_intN_t.
No functional changes.
interrupts/sec -- not the other way around. Caught by yamt.
When I can confirm that it won't lock the chip up on the models claimed
to be problematic, I'll probably adjust the packet timers a bit further
to see if I can get latency down under low load. But this should be
better.
transitioning a device to or from D3hot, 200us to or from D2, and no wait
for D1 transitions. Update pci_set_powerstate_int to match the spec,
rather than naively waiting 1ms after every state transition.
XXX: ahc_suspend panics here so suspend calls ahc_shutdown and resume does
nothing.
This fixes a hangup and subsequent panic which occured when the shutdown hooks
were called and /afterwards/ the sd suspend handler tried to flush caches
through an already shut down ahc.
instead of directly calling the pcn_79c970_mediachange function, we
must initialize sc->sc_mii.mii_ifp so that this last function is
passed a valid parameter.
Fixes a panic in pcn_79c970_mediachange that arose immediately when
trying to use this interface due to a NULL pointer dereference.
Hi dyoung@!
handling, ether_mediastatus() and ether_mediachange(). Check for
a non-ENXIO error return from mii_mediachg(). (ENXIO indicates
that a PHY is suspended.)
This patch shrinks the source code size by 979 lines. There was
a 5100-byte savings on the NetBSD/i386 kernel configuration, ALL.
I have made a few miscellaneous changes, too:
gem(4): use LIST_EMPTY(), LIST_FOREACH().
mtd(4): handle media ioctls, for a change!
axe(4): do not track link status in sc->axe_link any longer
nfe(4), aue(4), axe(4), udav(4), url(4): do not reset all PHYs
on a change of media
Except for the change to mtd(4), no functional changes are intended.
XXX This patch affects more architectures than I can feasibly
XXX compile and run. I have compiled macppc, sparc64, i386. I
XXX have run the patches on i386 boxen with bnx(4) and sip(4).
XXX Compiling and running on evbmips (MERAKI, ADM5120) is in
XXX progress.
Added support to create/remove hot-spare, pass-through disks.
Added support to create/remove volume sets.
Added support to show information about physical disks, even if they
are marked unused, hot-spares or pass-through.
sd(4) devices are attached/detached automagically when a pass-through
disk or volume set is created/removed... thanks scsipi(9) and cube@
for hints.
a pointer to that struct, so that we cannot assign pointers of
arbitrary type to cardbus_chipset_tag_t. Tweak cbb(4) to accomodate
this change.
Make Cardbus_conf_read() and Carbus_conf_write() pass the right
arguments to cardbus_functions->cardbus_conf_{read,write}() for a
change.
Let's hope this stops the crash in cardbus_function_enable() that
macallan@ reported to me.
This allows cats to override the BIOS (aka ABLE) settings, which enable
native mode, but doesn't route the interrupts correctly.
Discussed last year on tech-kern and port-cats.
Merge bnx_if_stop() and bnx_stop(). Handle bnx_stop(, 1) by doing
a reset.
Protect the bnx_stop() call in bnx_detach() with splnet().
Thanks to joerg@ for suggesting the above.
In bnx_stop(), deactivate the PHYs with mii_down(). Return right
away if !IFF_RUNNING.
Use LIST_EMPTY().
In bnx_ifmedia_upd(), propagate all mii_mediachg() return codes to
the caller except for ENXIO, which just means that the PHY is
suspended. In bnx_init(), propagate bnx_ifmedia_upd() return codes
to the caller.
In bnx_intr(), replace a common subexpression with a variable,
'sblk'.
In bnx_tick(), let the MII bus keep ticking after the link is up:
check link status and exit after calling mii_tick(), not before.
both pci and cardbus attachments with CFATTACH_DECL_NEW(). Access
the softc through the device_t using device_private().
While I'm here, change a couple of KASSERT()s about the Rx buffer
length to a warning.
This way we avoid a conflict with PCI resources on some Sun graphics cards
which have firmware that likes to put memory resources at low addresses.
For instance, if we have 1MB framebuffer and registers at 0x30000 we'll
get the registers when mmap()ing 0x30000 until someone tries to mmap(0),
then we'll get framebuffer memory for the entire 1st MB.
This needs an ioctl() to switch between fb-at-0 and PCI ranges.
Add if_set_sadl() that both sets the link-layer address length and
replaces the current link-layer address with a new one, and use it
throughout the tree.
of this entire device tree:
pci0 at mainbus0
elansc0 at pci0
gpio0 at elansc0
cbb0 at pci0
cardslot0 at cbb0
cardbus0 at cardslot0
pcmcia0 at cardslot0
cbb1 at pci0
cardslot1 at cbb1
cardbus1 at cardslot1
rtw0 at cardbus1
pcmcia1 at cardslot1
sip0 at pci0
nsphyter0 at sip0
sip1 at pci0
nsphyter1 at sip1
Whew!
the VT8231-IDE's native mode only works with irq 14/15, and cannot be
programmed to use a single native PCI irq alone. So we install an interrupt
handler for each channel, as in compatibility mode.
This behaviour has to be activated by the "use-compat-native-irq" property,
otherwise the driver works as before.
They do not seem well-justified according to anyone's understanding
of what they really do, and it seems especially inappropriate to
call them at attach- and resume-time.
get rid of SIP_DECL() and reduce #ifdef DP83820 code. Next step
is to move a bunch of shared code to a new file (if_sipcom.c, say)
and compile it *once*.
While I am here, add suspend/resume handling to sip(4) and to
gsip(4).
Tested with the NatSemi sip(4) on the Soekris net4521. I don't
have any gsip(4) to test with, and it seems that the few holders
of gsip(4) in the world keep them in their attic, anyway.
82571 manual and Intel Application Note 450. Previously, we were setting
RADV and TIDV/TADV values that didn't make any sense given the enormous
ITR value we were setting (well outside the range recommended by Intel
and quite possibly rejected silently by the chip as junk) and setting
RADV without setting RDTR, which is explicitly documented as having no
effect.
A considerable performance improvement is achieved for TCP and UDP at
gigabit speed. I need to revisit this to deal with the timer ticks
being 4X as long when the chip's in 100mbit mode, and to set values
for the older chips' interrupt timers that are more like what the
appnote recommends. This should help for 82543 and newer, though.
- malloc(9) -> kmem(9) now that most of the bio code doesn't need to run
on interrupt context.
- Reduce code that runs in interrupt context to a small part in
arc_msgbuf() and is protected by arc_lock()/arc_unlock().
Reviewed and help by ad@.
break functionality. I've tested this on a PCIE R423 (X800).
- In drm_drv.c, check that the requested context lock matches the holder
of the lock.
- Unify radeon offset checking. (r300_cmdbuf.c, radeon_drv.h, radeon_state.c)
[Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697]
NOTE: There is another AGP fix that I didn't have time to merge
that I thought might help with getting this to work on macppc.
Contact me if you're interested. Hi macallan@! ;)
radeon_cp.c, radeon_drv.h: (GIT id: bb5f2158dbd30dbbffa3881fac75b71d71ecaaf9)
- set the address to access the aperture on the CPU side correctly
[This code relied on the CPU and GPU address for the aperture being the same,
On some r5xx hardware I was playing with I noticed that this isn't always true.
I wonder if this will fix some of those r4xx DRI issues we've seen in the past.]
- Commit the ring after earch partial texture. (radeon_state.c)
(GIT ID: ac8406420ea80ffe5ccaadc1ff0124f95709a23d)
[Commit the ring after each partial texture upload blit.
This makes sure each blit starts as early as possible, which may improve
texture upload performance in some cases.]
If anyone's having any issues in particular--especially those which
can be _teased apart from AGP driver issues--please let me know
and I'll investigate. Thanks. There are also tons of fixes for the i915,
but I don't want to change too much at once.
this fixes a panic with debugging options.
- Do not use a callout to refresh sensor data, and make it available
every time someone requests it.
- Enable ENVSYS_FMONSTCHANGED for notifications in the volumes.
(nForce 2/3/4).
nfsmb(4) is now properly working on newer MCPs, tested by wiz@ on MCP55:
nfsmbc0 at pci0 dev 1 function 1: NVIDIA nForce MCP55 SMBus Controller (rev. 0xa2)
nfsmb0 at nfsmbc0 SMBus 1
iic0 at nfsmb0: I2C bus
spdmem0 at iic0 addr 0x51
spdmem0: DDR2 SDRAM memory, data ECC, 1024MB, 667MHz, PC2-5300
spdmem0: 14 rows, 10 cols, 2 ranks, 4 banks/chip, 3.00ns cycle time
spdmem0: voltage SSTL 1.8V, refresh time 7.8us (self-refreshing)
nfsmb1 at nfsmbc0 SMBus 2
iic1 at nfsmb1: I2C bus
This will not work until (at the very least) we map the memory properly
(MMIO/VRAM BARs are 64-bit)--some of the values in the configuration
space may be different. I will discuss this with others, and maybe
it will work someday.
consulted indicated that this ID is an R430 (including xf86-video-ati).
PCI_PRODUCT_ATI_RADEON_R430_554F (primary)
PCI_PRODUCT_ATI_RADEON_R430_556F (secondary)
vga0 at pci1 dev 0 function 0: ATI Technologies product 0x554f (rev. 0x00)
ATI Technologies product 0x556f (miscellaneous display) at pci1 dev 0 function 1 not configured
interrupts while attaching uhci. Fixes recent problems with uvm_fault
during uhci attach, which appear to be caused by a pending interrupt
left over from the device while it was operating in legacy support mode
under the control of the BIOS.
Patch by joerg@ because his was better than mine.
an Atheros WLAN. That generates a CB_SOCKET_EVENT_CSTS event on
the bridge. The event isn't interesting to pccbb(4), so we used
to ignore the interrupt. Now, let the child devices try to handle
the interrupt, instead. The Atheros NIC produces interrupts more
reliably, now: used to be that it would only interrupt if the driver
avoided powering down the NIC's cardslot, and then the NIC would
only work after it was reset a second time.
Let the TI1420 PCI-Cardbus bridge do burst reads from the primary
(PCI) bus. This ought to improve Tx performance on Cardbus NICs.
This optimization may apply to other TI bridges, but I only have
a datasheet for the TI1420. :-/
Activate PCI Parity Error and System Error reporting on PCI-Cardbus
bridges.
To avoid data destruction, set the Master Abort mode to 1. Stops
the bridge from silently discarding writes from the secondary bus
to the primary bus (Cardbus writes to PCI). Also, stops the bridge
from fulfilling a read by a bus master on the secondary bus that
failed on the primary bus with 0xffffffff (Cardbus reads from PCI).
Now the bus will indicate an error condition (SERR) instead of
silently destroying/corrupting data.
Forward system error indications from the secondary to the primary
bus. Detect parity errors on the secondary.
Set a Cardbus card's Latency Timer to something reasonable, according
to the Cardbus card's Minimum Grant and the bandwidth available on
the PCI bus. Restore the Latency Timer when re-enabling a card
(e.g., after power reactivation).
transaction to 8. value 32 triggers occational watchdog() Tx
timeout when higher system load. This symptom is observed in
ipforwarding across two PCI devices case so far, and it remains
unidentified what really happens for Tx DMA activity. 16 seems
ok, 8 is conservative and heuristic value. may need more adjustment
work in other parts.
http://mail-index.netbsd.org/tech-kern/2007/11/09/0001.html
sysmon_envsys_create() and sysmon_envsys_destroy() were added to
create/destroy sysmon_envsys objects (and its TAILQ/LIST for sensors/events).
sysmon_envsys_sensor_attach() and sysmon_envsys_sensor_detach() were
added to attach/detach sensors to a specified sysmon_envsys device.
The events framework is now per device and configurable via the
ENVSYS_SETDICTIONARY ioctl or /etc/envsys.conf and envstat(8).
Update all users and documentation to reflect these changes.
So far it supports some acceleration ( copies and rectangle fills ) but
no video mode programming at all.
Known problems:
- tested only on macppc
- matches only one r128 chip out of ca. 30
- character drawing is unaccelerated
- no attempt is made to restore the console when X exits
If you have a system where it doesn't get one and you still want pcic,
you can just disable cbb. This check is invalid as soon as the PCI
interrupt register is not used and broke on my Dell Latitude for that
reason.
xtraeme