Mio
45f22085f5
Update comments
2023-03-28 21:17:01 +08:00
Takacs, Philipp
8b2c477578
clear the TLB cache in uc_ctl_flush_tlb
...
uc_ctl_flush_tlb implies that the tlb is flushed. This change adds
UC_CTL_TLB_FLUSH which clears the TLB and set the uc_ctl_flush_tlb
alias to UC_CTL_TLB_FLUSH. Also adds a uc_ctl_flush_tb alias for
UC_CTL_TB_FLUSH.
2023-03-28 14:11:41 +02:00
Takacs, Philipp
e96ac42b2e
Remove MMU hacks
...
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.
The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d
add virtuall tlb
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this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4
difference between stop_request and quit_request
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quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.
stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
Nguyen Anh Quynh
eb118528b1
rename memory_mapping() to find_memory_region() and simplify mem_map()
2023-02-06 17:59:16 +08:00
Nguyen Anh Quynh
6e9c6aea5f
bump version to 2.0.2
2023-02-04 13:00:58 +08:00
mio
bdd9f4fa9a
Bump version to 2.0.1
2022-11-01 10:06:22 +01:00
TSR Berry
442dd437e1
aarch64: Move FPCR and FPSR registers to not break compatibility
...
Co-authored-by: merry <git@mary.rs>
2022-10-14 17:31:20 +02:00
TSR Berry
12fd4fc086
aarch64: Add FPCR and FPSR registers
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Co-authored-by: merry <git@mary.rs>
2022-10-14 15:18:14 +02:00
mio
19d8876e23
Deep copy for arm cpu state
2022-10-01 00:14:08 +02:00
Mio
d6d57834b0
Format code
2022-07-23 19:27:37 +08:00
Mio
db8c04a07c
Fix value collision between UC_MODE_ARMBE8 and UC_MODE_ARM926
2022-07-04 22:35:16 +08:00
lazymio
6d61aec82f
Format code
2022-06-02 14:46:26 +02:00
lazymio
fdd129fd30
Remember the regions a hook has intrumented and clear cache on deletion
2022-06-02 14:46:02 +02:00
lazymio
e5126f17f1
Bump version in bindings
2022-05-23 12:34:09 +02:00
lazymio
b827ebf4c3
Format code
2022-05-07 00:30:18 +02:00
lazymio
345b63ee96
Only exit TB if pc is within the memory range
2022-05-07 00:16:31 +02:00
Eric Poole
cfee2139a0
TriCore Support ( #1568 )
...
* TriCore Support
python sample
* Update sample_tricore.py
Correct attribution
* Update sample_tricore.py
Fixed byte code to execute properly.
* Update sample_tricore.py
Removed testing artifact
* Added tricore msvc config-file.h
* Added STATIC to tricore config and added helper methods to symbol file generation.
* Update op_helper.c
Use built in crc32
* Fix tricore samples and small code blocks are now handled properly
* Add CPU types
* Generate bindings
* Format code
Co-authored-by: lazymio <mio@lazym.io>
2022-04-29 23:11:34 +02:00
lazymio
4e22744679
Support flushing translation blocks and flush when we don't need count hook
2022-04-26 01:17:58 +02:00
lazymio
8fd9ee3dd0
Bump unicorn version
2022-04-17 16:47:37 +02:00
lazymio
c379d1bfe4
Format code
2022-04-16 17:50:12 +02:00
lazymio
b136f08f2d
Check CPU model for uc_ctl
2022-04-16 17:49:47 +02:00
Ilya Leoshkevich
28c4c665f0
Add "holes" to where the removed x86 registers used to be
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A number of x86 registers were removed for #1440 , causing a change in
numbering for many other registers. This is causing inconveniences at
the moment, e.g. it's not possible to use the Unicorn2 shared library
as a drop-in replacement for the Unicorn1 one.
Restore the old numbering.
Fixes #1492 .
2022-03-22 11:31:58 +01:00
lazymio
1eeab7bb02
Format code
2022-03-06 23:40:50 +01:00
lazymio
09b15e9071
Fix exits wrongly cleared in nested uc_emu_start
2022-03-06 23:40:34 +01:00
lazymio
ce932e4c28
Update comments for uc_cb_insn_sys_t
2022-03-05 22:42:41 +01:00
lazymio
e5207a1363
Implement UC_HOOK_INSN for aarch64 MRS/MSR/SYS/SYSL
2022-02-27 15:28:31 +01:00
Bet4
504b31b928
Update constants of bindings
2022-02-19 21:24:40 +08:00
lazymio
27ef63cc8d
Add UC_PPC_REG_CR
2022-02-15 22:07:53 +01:00
lazymio
16e9efa4f5
Bump version
2022-02-13 09:56:10 +01:00
lazymio
2a84e33f03
Fix possible leak in hooks
2022-02-12 16:28:43 +01:00
lazymio
58fc952230
Remove armeb-softmmu and aarch64eb-softmmu
2022-02-12 14:15:54 +01:00
lazymio
acbc134f46
Fixed width fields
2022-02-11 22:18:52 +01:00
lazymio
3e6665db00
Implement coprocessor register read/write for arm64
2022-02-11 22:13:01 +01:00
lazymio
8bc1489210
Implement coprocessor register read/write for arm
2022-02-11 21:45:37 +01:00
mio
7095605607
Merge branch 'dev' into systemz
2022-01-18 21:10:55 +01:00
mio
28e791a37f
Add debug tracing feature
...
It's disabled by default, use -DUNICORN_TRACER=on to enable it
2022-01-18 19:35:43 +01:00
lazymio
a5ceca6d51
Remove the static variable in flatviews_init
...
Or we may get an invalid old (and free-ed) uc instance reference
2022-01-15 22:11:14 +01:00
lazymio
441afe17e6
Add psw.mask register
2022-01-10 15:34:04 +01:00
lazymio
71f044ca50
Merge branch 'dev' into s390x
2022-01-10 15:17:42 +01:00
lazymio
36afa1022c
More PPC registers
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Add FPR0-31, CR0-7, LR, CTR, MSR, XER, FPSCR for PPC
Add a test for ppc32 float point
2022-01-10 15:16:10 +01:00
lazymio
4567b4a790
Fix the wrong arm cpu index
2022-01-05 21:57:46 +01:00
lazymio
d854e22301
Add x87 FPU registers #1524
2022-01-04 21:12:12 +01:00
mio
a38151bf77
Make s390x skey work
2021-12-27 23:19:17 +01:00
mio
faa689c0f0
Merge systemz to the latest uc2 codebase
2021-12-26 22:58:32 +01:00
lazymio
7bb756249a
Better design of cpuid instruction hook
2021-12-22 20:36:56 +01:00
Nguyen Anh Quynh
b042a6a01d
add missing files
2021-12-06 04:28:13 +08:00
Nguyen Anh Quynh
97b92d8861
initial systemz support
2021-12-06 04:19:37 +08:00
lazymio
3020d7b82a
Fix wrong m68k enums
2021-12-04 23:20:46 +01:00
