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Author SHA1 Message Date
Robert Xiao
b041345a73 Fix RISCV test_riscv32_fp_move test 
RISCV FP registers are 64-bit in size, even in 32-bit mode, because they can
hold doubles. The test even uses the double-precision instruction fmv.d. Thus,
the reads should be reading 64-bit registers.
 2023-06-16 15:23:43 -07:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost. 
Single reg_read/reg_write is now about 25% faster.
 2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication. 
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
 2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs. 
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
 2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
mio
fa1f26138e
Fix missing stdint 
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
 2023-06-10 23:48:18 +02:00
mio
49ccbde2d0
Leave out essential files 
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
 2023-06-10 23:44:05 +02:00
mio
8dffbc159c
Add uc_ctl_get/set_tcg_buffer_size 
We still need this API because the virtual memory address space of

32 bits os is only 4GB and we default need 1G per instance

Credits to @ZehMatt for original idea

Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
 2023-06-10 23:36:02 +02:00
mio
f8c7969d65
Revert "Add uc_ctl_get/set_tcg_buffer_size" 
This reverts commit 3145e3c426 because not
properly co-authoer-ed.
 2023-06-10 23:29:56 +02:00
mio
3145e3c426
Add uc_ctl_get/set_tcg_buffer_size 2023-06-10 16:08:29 +02:00
mio
5057f9925b
Fix typo 2023-06-10 15:26:29 +02:00
mio
9de80cb625
Correct calling convention 2023-06-10 15:03:59 +02:00
mio
3d5b2643f0
Support demand paging via closures and seh 
Reverts 12a79192ee which exploits normal tcg mechanism

This uses a trampoline to pass extra data to seh handlers
 2023-06-10 14:04:56 +02:00
lazymio
7b4dc569cc
Merge pull request #1836 from PhilippTakacs/UC_MEM_WRITE_PROT 
fix UC_MEM_WRITE_PROT callback
 2023-05-25 22:41:58 +02:00
lazymio
cd11aed350
Merge pull request #1837 from tunz/apt-update 
Run apt update in nuget publishing workflow
 2023-05-25 22:41:18 +02:00
Choongwoo Han
67f0386299
Add apt update 2023-05-23 13:18:57 -07:00
Takacs, Philipp
fa457a3a97 fix UC_MEM_WRITE_PROT callback 
callbacks work on the physical address.
 2023-05-22 15:38:37 +02:00
mio
994813a0e5
Also check cpu->stopped 2023-05-19 23:24:42 +02:00
mio
be2f092179
Merge remote-tracking branch 'phl/issuevtlb' into dev 2023-05-19 23:22:23 +02:00
mio
a24e53d794
Rebuild flags after writing to cp registers 
This is buggy as this momemt per https://github.com/unicorn-engine/unicorn/issues/1789#issuecomment-1546807410

We need either doc this or save more information for a context
 2023-05-14 13:35:31 +02:00
Takacs, Philipp
4a7b3b7a3a fixup! load_helper only call cpu_loop_exit() when emulation is running 2023-05-12 12:36:16 +02:00
lazymio
f65f8f8380
Merge pull request #1830 from nneonneo/fix-python-ctl 
Fix sample_ctl.py
 2023-05-11 13:10:01 +02:00
Robert Xiao
06a76e98c4 Add __repr__ to all ctypes.Structure subclasses 2023-05-10 12:58:25 -07:00
Takacs, Philipp
073c4b74ca load_helper only call cpu_loop_exit() when emulation is running 
The load_helper is sometimes called from register writes. When the load
fails check if emulation is running before jump out of the emulated code.
 2023-05-09 14:58:40 +02:00
lazymio
1d9c5c7653
Merge pull request #1832 from PhilippTakacs/cleanup 
Some clean-up for the vtlb merge
 2023-05-09 14:43:07 +02:00
Takacs, Philipp
227e578660 move typedef definition of enum uc_mem_type 
forword references to enum types are forbidden in C. Also C++ will
not build if this is used
 2023-05-08 15:38:43 +02:00
Takacs, Philipp
54870cca0e remove unused function cmp_vaddr 2023-05-08 15:32:58 +02:00
Robert Xiao
d27ca4530b Minor Python fixes. 
- Match the types of UC_HOOK_CODE_CB and UC_HOOK_INSN_SYS_CB to C
- Avoid building a new namedtuple class in every call to _hook_insn_sys_cb
 2023-05-07 09:08:20 -07:00
Robert Xiao
a998231a0e Fix sample_ctl.py. 
Commit 640251e1aa added a size parameter to uc_hook_tcg_op_2, but this was not
reflected in the Python bindings.

Commit fbf4078d65 added a len parameter to ctl_remove_cache, but this was not
reflected in sample_ctl.py.
 2023-05-07 09:08:20 -07:00
lazymio
bde3cd7dae
Merge pull request #1812 from ks0777/ctl_rust 
add rust bindings for uc_ctl
 2023-04-24 16:25:34 +02:00
lazymio
98b9373937
Merge pull request #1826 from PhilippTakacs/int128 
use int128_get64 in memory_unmap
 2023-04-19 13:50:43 +02:00
Takacs, Philipp
7bb1501bc2 use int128_get64 in memory_unmap 
This fixes build errors introduced by bbbc7856ac
 2023-04-17 17:48:58 +02:00
Mio
bbbc7856ac
Invalidate tb cache once mapping is removed 2023-04-12 20:56:54 +08:00
lazymio
2849bc010a
Merge pull request #1816 from kassane/clang-getpagesize 
Clang/MinGW getpagesize
 2023-04-10 17:49:55 +08:00
Philipp Takacs
a9f0dabc64 rust add tlb callback 2023-04-05 18:57:22 +02:00
Philipp Takacs
0729dc0312 rust update uc_ctl_flush_tlb and add uc_ctl_tlb_mode 2023-04-05 18:57:15 +02:00
Kevin Schneider
5ff654c77b add rust bindings for uc_ctl 2023-04-05 18:48:39 +02:00
Matheus C. França
2d94e30988 Fix clang/mingw - missing getpagesize 
Based on msys2-packages patch:
https://github.com/msys2/MINGW-packages/pull/10543
 2023-04-03 11:08:27 -03:00
lazymio
51a5b68b50
Merge pull request #1746 from PhilippTakacs/virtual_tlb 
Virtual tlb
 2023-03-28 21:17:24 +08:00
Mio
45f22085f5
Update comments 2023-03-28 21:17:01 +08:00
Mio
d403a0346e
Update FAQ 2023-03-28 21:16:19 +08:00
Mio
0ba69d6b2f Add tlb_mode for python 2023-03-28 14:20:55 +02:00
Mio
9c01d23ed3 Update bindings const 2023-03-28 14:20:55 +02:00
Takacs, Philipp
9f00bb2ed5 update faq 
add How can I interact with MMU/TLB
 2023-03-28 14:20:32 +02:00
Takacs, Philipp
8b2c477578 clear the TLB cache in uc_ctl_flush_tlb 
uc_ctl_flush_tlb implies that the tlb is flushed. This change adds
UC_CTL_TLB_FLUSH which clears the TLB and set the uc_ctl_flush_tlb
alias to UC_CTL_TLB_FLUSH. Also adds a uc_ctl_flush_tb alias for
UC_CTL_TB_FLUSH.
 2023-03-28 14:11:41 +02:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks 
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
 2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb 
this virtuall tlb allows to use mmu indipendent of the architectur
 2023-03-28 13:50:11 +02:00
Takacs, Philipp
759d694e24 sample to use the softmmu 2023-03-28 13:50:11 +02:00
Takacs, Philipp
901034577a i386 call internal helper on special porpese register write 
Some registers writes have side effects. i.e. write to cr3 flush the tlb,
if the PG bit is set.
 2023-03-28 13:50:11 +02:00
Takacs, Philipp
7f1eb4532d add basic mmu tests 
Some simple tests for diffrent mmu.
Basicly add some tlb entries, enable the mmu try to read from virtual address

The aarm64 test was provided by imre-kis-arm in #1718
 2023-03-28 13:50:11 +02:00