Commit Graph

348 Commits

Author SHA1 Message Date
mio
67f08b1c27
Bump version and generate bindings 2024-09-21 23:00:57 +08:00
mio
87c0b86248
Format code 2024-09-21 17:59:23 +08:00
lockbox
321de00f36 [typo]: Correctly document address parameter in mem hook callbacks 2024-03-18 17:51:35 -04:00
lazymio
822bb527f3
M1 W^X fully supported 2024-02-12 00:10:44 +08:00
lazymio
43597af0ed
Merge pull request #1833 from nneonneo/rework-java-api
Rework the Java bindings
2023-12-25 19:53:45 +08:00
lazymio
6801e156aa
Format code 2023-08-06 21:53:42 +08:00
Takacs, Philipp
df18756234 implement uc_mem_unmap with snapshots
still has todos and need tests
2023-07-11 11:51:44 +02:00
Takacs, Philipp
716c8f1c4c handle snapshots over context_save context_restore 2023-07-11 11:51:44 +02:00
Takacs, Philipp
e54cf7ee03 find_ram_offset optimization
The ram_offset allocator searches the smalest gap in the ram_offset address space.
This is slow especialy in combination with many allocation (i.e. snapshots). When
it is known that there is no gap, this is now optimized.
2023-07-11 11:51:44 +02:00
Takacs, Philipp
80bd825420 implement simple memory snapshot mechanismus
Uses Copy on Write to make it posible to restore the memory state after a snapshot
was made. To restore all MemoryRegions created after the snapshot are removed.
2023-07-11 11:51:40 +02:00
Takacs, Philipp
065af19dc5 use address_space_translate to find memory mapping
first version has bugs
2023-07-11 11:47:50 +02:00
Robert Xiao
77d4a1d8b1 Fix definition of uc_version 2023-06-17 14:19:10 -07:00
Robert Xiao
2b80ab425b Return new UC_ERR_OVERFLOW instead of UC_ERR_NOMEM when reg buffer is too small 2023-06-16 15:30:59 -07:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost.
Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
mio
49ccbde2d0
Leave out essential files
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:44:05 +02:00
mio
8dffbc159c
Add uc_ctl_get/set_tcg_buffer_size
We still need this API because the virtual memory address space of

32 bits os is only 4GB and we default need 1G per instance

Credits to @ZehMatt for original idea

Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:36:02 +02:00
mio
f8c7969d65
Revert "Add uc_ctl_get/set_tcg_buffer_size"
This reverts commit 3145e3c426 because not
properly co-authoer-ed.
2023-06-10 23:29:56 +02:00
mio
3145e3c426
Add uc_ctl_get/set_tcg_buffer_size 2023-06-10 16:08:29 +02:00
mio
3d5b2643f0
Support demand paging via closures and seh
Reverts 12a79192ee which exploits normal tcg mechanism

This uses a trampoline to pass extra data to seh handlers
2023-06-10 14:04:56 +02:00
Takacs, Philipp
227e578660 move typedef definition of enum uc_mem_type
forword references to enum types are forbidden in C. Also C++ will
not build if this is used
2023-05-08 15:38:43 +02:00
Mio
45f22085f5
Update comments 2023-03-28 21:17:01 +08:00
Takacs, Philipp
8b2c477578 clear the TLB cache in uc_ctl_flush_tlb
uc_ctl_flush_tlb implies that the tlb is flushed. This change adds
UC_CTL_TLB_FLUSH which clears the TLB and set the uc_ctl_flush_tlb
alias to UC_CTL_TLB_FLUSH. Also adds a uc_ctl_flush_tb alias for
UC_CTL_TB_FLUSH.
2023-03-28 14:11:41 +02:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb
this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4 difference between stop_request and quit_request
quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.

stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
Nguyen Anh Quynh
eb118528b1 rename memory_mapping() to find_memory_region() and simplify mem_map() 2023-02-06 17:59:16 +08:00
Nguyen Anh Quynh
6e9c6aea5f bump version to 2.0.2 2023-02-04 13:00:58 +08:00
mio
bdd9f4fa9a
Bump version to 2.0.1 2022-11-01 10:06:22 +01:00
TSR Berry
442dd437e1
aarch64: Move FPCR and FPSR registers to not break compatibility
Co-authored-by: merry <git@mary.rs>
2022-10-14 17:31:20 +02:00
TSR Berry
12fd4fc086
aarch64: Add FPCR and FPSR registers
Co-authored-by: merry <git@mary.rs>
2022-10-14 15:18:14 +02:00
mio
19d8876e23
Deep copy for arm cpu state 2022-10-01 00:14:08 +02:00
Mio
d6d57834b0
Format code 2022-07-23 19:27:37 +08:00
Mio
db8c04a07c
Fix value collision between UC_MODE_ARMBE8 and UC_MODE_ARM926 2022-07-04 22:35:16 +08:00
lazymio
6d61aec82f
Format code 2022-06-02 14:46:26 +02:00
lazymio
fdd129fd30
Remember the regions a hook has intrumented and clear cache on deletion 2022-06-02 14:46:02 +02:00
lazymio
e5126f17f1
Bump version in bindings 2022-05-23 12:34:09 +02:00
lazymio
b827ebf4c3
Format code 2022-05-07 00:30:18 +02:00
lazymio
345b63ee96
Only exit TB if pc is within the memory range 2022-05-07 00:16:31 +02:00
Eric Poole
cfee2139a0
TriCore Support (#1568)
* TriCore Support

python sample

* Update sample_tricore.py

Correct attribution

* Update sample_tricore.py

Fixed byte code to execute properly.

* Update sample_tricore.py

Removed testing artifact

* Added tricore msvc config-file.h

* Added STATIC to tricore config and added helper methods to symbol file generation.

* Update op_helper.c

Use built in crc32

* Fix tricore samples and small code blocks are now handled properly

* Add CPU types

* Generate bindings

* Format code

Co-authored-by: lazymio <mio@lazym.io>
2022-04-29 23:11:34 +02:00
lazymio
4e22744679
Support flushing translation blocks and flush when we don't need count hook 2022-04-26 01:17:58 +02:00
lazymio
8fd9ee3dd0
Bump unicorn version 2022-04-17 16:47:37 +02:00
lazymio
c379d1bfe4
Format code 2022-04-16 17:50:12 +02:00
lazymio
b136f08f2d
Check CPU model for uc_ctl 2022-04-16 17:49:47 +02:00
Ilya Leoshkevich
28c4c665f0 Add "holes" to where the removed x86 registers used to be
A number of x86 registers were removed for #1440, causing a change in
numbering for many other registers. This is causing inconveniences at
the moment, e.g. it's not possible to use the Unicorn2 shared library
as a drop-in replacement for the Unicorn1 one.

Restore the old numbering.

Fixes #1492.
2022-03-22 11:31:58 +01:00
lazymio
1eeab7bb02
Format code 2022-03-06 23:40:50 +01:00
lazymio
09b15e9071
Fix exits wrongly cleared in nested uc_emu_start 2022-03-06 23:40:34 +01:00
lazymio
ce932e4c28
Update comments for uc_cb_insn_sys_t 2022-03-05 22:42:41 +01:00
lazymio
e5207a1363
Implement UC_HOOK_INSN for aarch64 MRS/MSR/SYS/SYSL 2022-02-27 15:28:31 +01:00