Commit Graph

2853 Commits

Author SHA1 Message Date
lazymio
30bc08611b
Add a unit test for #1717 2023-08-06 21:53:04 +08:00
lazymio
c889258d8e
Avoid overwriting tmp0 2023-08-06 21:25:37 +08:00
lazymio
0619deeafd
Merge pull request #1861 from basavesh/dev
Backport qemu/qemu@75b208c
2023-08-04 11:18:49 +08:00
basavesh
cf5e75953d Backport qemu/qemu@75b208c
target/i386: fix operand order for PDEP and PEXT

For PDEP and PEXT, the mask is provided in the memory (mod+r/m)
operand, and therefore is loaded in s->T0 by gen_ldst_modrm.
The source is provided in the second source operand (VEX.vvvv)
and therefore is loaded in s->T1. Fix the order in which
they are passed to the helpers.
2023-08-03 13:12:39 +02:00
lazymio
6e97e59f54
Fix building on Apple Sillicon 2023-08-03 13:17:26 +08:00
lazymio
6074150ebe
Merge pull request #1850 from mlgiraud/fix/clippy_warnings
Fix clippy warnings
2023-07-26 19:53:52 +08:00
Mark Giraud
c43ab92326
fix: Add missing Copy derive 2023-07-26 09:58:09 +02:00
Mark Giraud
5a5b1bbb05
fix: update bitflags dependency and fix flippy warnings 2023-07-26 09:55:04 +02:00
lazymio
239766aa66
Merge pull request #1849 from mlgiraud/fix/rust_compiler_warnings
Fix rust compiler warnings
2023-07-26 15:35:33 +08:00
lazymio
1e0930d478
Merge pull request #1847 from lockbox/dev
Add CpuModel's for architectures to rust bindings
2023-07-26 15:35:01 +08:00
lazymio
34cca20877
Merge pull request #1848 from PhilippTakacs/vtlb-perms
vtlb only cache access permisions required for the operation
2023-07-26 15:32:45 +08:00
Mark Giraud
546561f3cc
fix: Remove unnecessary use statement that causes warnings 2023-07-18 11:49:18 +02:00
Takacs, Philipp
f6cfe1092b vtlb only cache access permisions required for the operation
see #1845
2023-07-17 12:54:38 +02:00
lockbox
2f2bf8d96f add cpu model to architectures for rust bindings 2023-07-13 13:58:14 -04:00
lockbox
84fe5d1756 expose ffi in rust bindings 2023-07-13 13:57:04 -04:00
lazymio
e88264c658
Merge pull request #1820 from PhilippTakacs/cow
add memory snapshots
2023-07-11 19:24:00 +08:00
Takacs, Philipp
ab5938b3f6 Update CREDITS.TXT 2023-07-11 11:51:44 +02:00
Takacs, Philipp
df18756234 implement uc_mem_unmap with snapshots
still has todos and need tests
2023-07-11 11:51:44 +02:00
Takacs, Philipp
716c8f1c4c handle snapshots over context_save context_restore 2023-07-11 11:51:44 +02:00
Takacs, Philipp
e54cf7ee03 find_ram_offset optimization
The ram_offset allocator searches the smalest gap in the ram_offset address space.
This is slow especialy in combination with many allocation (i.e. snapshots). When
it is known that there is no gap, this is now optimized.
2023-07-11 11:51:44 +02:00
Takacs, Philipp
550265f3c1 snapshot benchmark
simple benchmark for the snapshots
2023-07-11 11:51:44 +02:00
Takacs, Philipp
80bd825420 implement simple memory snapshot mechanismus
Uses Copy on Write to make it posible to restore the memory state after a snapshot
was made. To restore all MemoryRegions created after the snapshot are removed.
2023-07-11 11:51:40 +02:00
Takacs, Philipp
065af19dc5 use address_space_translate to find memory mapping
first version has bugs
2023-07-11 11:47:50 +02:00
Takacs, Philipp
cd85f589a2 add memory_region_add_subregion_overlap 2023-07-11 11:47:50 +02:00
mio
aee4038526
Fix test_x86_0xff_lcall test 2023-07-07 18:50:55 +08:00
mio
2325f41ead
Add a unit test for a7a5d187e7 2023-06-30 20:28:59 +08:00
mio
a7a5d187e7
Backport 10b8eb94c0
target/i386: Verify memory operand for lcall and ljmp

These two opcodes only allow a memory operand.

Lacking the check for a register operand, we used the A0 temp

without initialization, which led to a tcg abort.
2023-06-30 20:21:56 +08:00
mio
75676eb0cd
Also rebuild flags for aarch32 2023-06-28 10:39:25 +08:00
Nguyen Anh Quynh
3bba11c402 remove all legacy DYNLOAD code 2023-06-22 12:19:06 +08:00
lazymio
c5ae96536b
Merge pull request #1835 from nneonneo/reg_ops2
Implement reg_{read,write}2 API
2023-06-17 21:47:26 +02:00
Robert Xiao
2b80ab425b Return new UC_ERR_OVERFLOW instead of UC_ERR_NOMEM when reg buffer is too small 2023-06-16 15:30:59 -07:00
Robert Xiao
b041345a73 Fix RISCV test_riscv32_fp_move test
RISCV FP registers are 64-bit in size, even in 32-bit mode, because they can
hold doubles. The test even uses the double-precision instruction fmv.d. Thus,
the reads should be reading 64-bit registers.
2023-06-16 15:23:43 -07:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost.
Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication.
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
mio
fa1f26138e
Fix missing stdint
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:48:18 +02:00
mio
49ccbde2d0
Leave out essential files
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:44:05 +02:00
mio
8dffbc159c
Add uc_ctl_get/set_tcg_buffer_size
We still need this API because the virtual memory address space of

32 bits os is only 4GB and we default need 1G per instance

Credits to @ZehMatt for original idea

Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:36:02 +02:00
mio
f8c7969d65
Revert "Add uc_ctl_get/set_tcg_buffer_size"
This reverts commit 3145e3c426 because not
properly co-authoer-ed.
2023-06-10 23:29:56 +02:00
mio
3145e3c426
Add uc_ctl_get/set_tcg_buffer_size 2023-06-10 16:08:29 +02:00
mio
5057f9925b
Fix typo 2023-06-10 15:26:29 +02:00
mio
9de80cb625
Correct calling convention 2023-06-10 15:03:59 +02:00
mio
3d5b2643f0
Support demand paging via closures and seh
Reverts 12a79192ee which exploits normal tcg mechanism

This uses a trampoline to pass extra data to seh handlers
2023-06-10 14:04:56 +02:00
lazymio
7b4dc569cc
Merge pull request #1836 from PhilippTakacs/UC_MEM_WRITE_PROT
fix UC_MEM_WRITE_PROT callback
2023-05-25 22:41:58 +02:00
lazymio
cd11aed350
Merge pull request #1837 from tunz/apt-update
Run apt update in nuget publishing workflow
2023-05-25 22:41:18 +02:00
Choongwoo Han
67f0386299
Add apt update 2023-05-23 13:18:57 -07:00
Takacs, Philipp
fa457a3a97 fix UC_MEM_WRITE_PROT callback
callbacks work on the physical address.
2023-05-22 15:38:37 +02:00
mio
994813a0e5
Also check cpu->stopped 2023-05-19 23:24:42 +02:00
mio
be2f092179
Merge remote-tracking branch 'phl/issuevtlb' into dev 2023-05-19 23:22:23 +02:00