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Fix building on Apple Sillicon

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lazymio 2023-08-03 13:17:26 +08:00
parent 6074150ebe
commit 6e97e59f54
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GPG Key ID: DFF27E34A47CB873
3 changed files with 12 additions and 3 deletions
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4
qemu/accel/tcg/cpu-exec-common.c
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@ -37,7 +37,9 @@ void cpu_reloading_memory_map(void)
void cpu_loop_exit(CPUState *cpu)
{
/* Unlock JIT write protect if applicable. */
tb_exec_unlock(cpu->uc->tcg_ctx);
if (cpu->uc->nested_level == 1) {
tb_exec_unlock(cpu->uc->tcg_ctx);
}
/* Undo the setting in cpu_tb_exec. */
cpu->can_do_io = 1;
siglongjmp(cpu->uc->jmp_bufs[cpu->uc->nested_level - 1], 1);

5
qemu/accel/tcg/cpu-exec.c
View File

@ -58,7 +58,10 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
UC_TRACE_START(UC_TRACE_TB_EXEC);
tb_exec_lock(cpu->uc->tcg_ctx);
ret = tcg_qemu_tb_exec(env, tb_ptr);
tb_exec_unlock(cpu->uc->tcg_ctx);
if (cpu->uc->nested_level == 1) {
// Only unlock (allow writing to JIT area) if we are the outmost uc_emu_start
tb_exec_unlock(cpu->uc->tcg_ctx);
}
UC_TRACE_END(UC_TRACE_TB_EXEC, "[uc] exec tb 0x%" PRIx64 ": ", itb->pc);
cpu->can_do_io = 1;

6
qemu/tcg/aarch64/tcg-target.inc.c
View File

@ -832,7 +832,11 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
{
unsigned h, l, r, c;
tcg_debug_assert(is_limm(limm));
// Unicorn Hack (wtdcode):
// I have no clue about this assert and it seems the logic here is same with QEMU at least 7.2.1
// That said, qemu probably suffers the same issue but maybe no one emulates mips on M1?
// Disabling this still passes all unit tests so let's go with it.
// tcg_debug_assert(is_limm(limm));
h = clz64(limm);
l = ctz64(limm);