Mayuresh Chitale ac66f2f0d1 target/riscv: pmp: Ignore writes when RW=01 ... As per the Priv spec: "The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved." However currently such writes are not ignored as ought to be. The combinations with RW=01 are allowed only when the Smepmp extension is enabled and mseccfg.MML is set. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231019065705.1431868-1-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-11-07 11:06:02 +10:00
..
insn_trans	target/riscv: rename ext_icboz to ext_zicboz	2023-11-07 11:02:17 +10:00
kvm	target/riscv/kvm/kvm-cpu.c: add missing property getters()	2023-11-07 11:02:17 +10:00
tcg	Add epmp to extensions list and rename it to smepmp	2023-11-07 11:06:02 +10:00
arch_dump.c	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu_bits.h	target/riscv: Add M-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
cpu_cfg.h	Add epmp to extensions list and rename it to smepmp	2023-11-07 11:06:02 +10:00
cpu_helper.c	target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu-param.h	target/riscv: Remove NB_MMU_MODES define	2023-03-13 06:44:37 -07:00
cpu-qom.h	target/riscv: add 'max' CPU type	2023-10-12 11:39:33 +10:00
cpu.c	target/riscv: pmp: Clear pmp/smepmp bits on reset	2023-11-07 11:06:02 +10:00
cpu.h	target/riscv: add riscv_cpu_accelerator_compatible()	2023-11-07 11:06:02 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	Add epmp to extensions list and rename it to smepmp	2023-11-07 11:06:02 +10:00
debug.c	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
debug.h	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
fpu_helper.c	riscv: Add support for the Zfa extension	2023-07-10 22:29:20 +10:00
gdbstub.c	target/riscv: rename ext_icsr to ext_zicsr	2023-11-07 11:02:17 +10:00
helper.h	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
insn16.decode	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00
insn32.decode	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: Introduce mmuidx_2stage	2023-05-05 10:49:50 +10:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c	target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
meson.build	target/riscv: move KVM only files to kvm subdir	2023-10-12 12:20:24 +10:00
monitor.c	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
op_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
pmp.c	target/riscv: pmp: Ignore writes when RW=01	2023-11-07 11:06:02 +10:00
pmp.h	target/riscv: pmp: Clear pmp/smepmp bits on reset	2023-11-07 11:06:02 +10:00
pmu.c	target/riscv/pmu: Restrict 'qemu/log.h' include to source	2023-08-31 19:47:43 +02:00
pmu.h	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c	target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion	2023-11-07 11:06:02 +10:00
sbi_ecall_interface.h	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
time_helper.c	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	accel/tcg: Replace CPUState.env_ptr with cpu_env()	2023-10-04 11:03:54 -07:00
vcrypto_helper.c	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
vector_helper.c	target/riscv: Fix vfwmaccbf16.vf	2023-10-12 12:50:13 +10:00
vector_internals.c	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:54 +10:00
vector_internals.h	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:55 +10:00
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
zce_helper.c	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00