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target/riscv: Simplify type conversion for CPURISCVState

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Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-09 15:13:28 +08:00 committed by Alistair Francis
parent 99c2f5c42a
commit bbb9fc2591
7 changed files with 31 additions and 44 deletions
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6
target/riscv/cpu.c
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@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
if (kvm_enabled()) {
kvm_riscv_set_irq(cpu, irq, level);
} else {
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
}
break;
case IRQ_S_EXT:
@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
kvm_riscv_set_irq(cpu, irq, level);
} else {
env->external_seip = level;
riscv_cpu_update_mip(cpu, 1 << irq,
riscv_cpu_update_mip(env, 1 << irq,
BOOL_TO_MASK(level | env->software_seip));
}
break;
@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
}
/* Update mip.SGEIP bit */
riscv_cpu_update_mip(cpu, MIP_SGEIP,
riscv_cpu_update_mip(env, MIP_SGEIP,
BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
} else {
g_assert_not_reached();

3
target/riscv/cpu.h
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@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
uint64_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
void *arg);

8
target/riscv/cpu_helper.c
View File

@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
*
* To solve this, we check and inject interrupt after setting V=1.
*/
riscv_cpu_update_mip(env_archcpu(env), 0, 0);
riscv_cpu_update_mip(env, 0, 0);
}
}
@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
}
}
uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
uint64_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
CPUState *cs = env_cpu(env);
uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
if (riscv_cpu_virt_enabled(env)) {

35
target/riscv/csr.c
View File

@ -991,15 +991,13 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
if (riscv_cpu_mxl(env) == MXL_RV32) {
env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
} else {
env->vstimecmp = val;
}
riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
return RISCV_EXCP_NONE;
@ -1008,10 +1006,8 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
return RISCV_EXCP_NONE;
@ -1044,8 +1040,6 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
if (riscv_cpu_virt_enabled(env)) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@ -1059,7 +1053,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
env->stimecmp = val;
}
riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
return RISCV_EXCP_NONE;
}
@ -1067,8 +1061,6 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
if (riscv_cpu_virt_enabled(env)) {
if (env->hvictl & HVICTL_VTI) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@ -1077,7 +1069,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
}
env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
return RISCV_EXCP_NONE;
}
@ -2212,7 +2204,6 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
uint64_t *ret_val,
uint64_t new_val, uint64_t wr_mask)
{
RISCVCPU *cpu = env_archcpu(env);
uint64_t old_mip, mask = wr_mask & delegable_ints;
uint32_t gin;
@ -2221,14 +2212,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
new_val |= env->external_seip * MIP_SEIP;
}
if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
get_field(env->menvcfg, MENVCFG_STCE)) {
/* sstc extension forbids STIP & VSTIP to be writeable in mip */
mask = mask & ~(MIP_STIP | MIP_VSTIP);
}
if (mask) {
old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
} else {
old_mip = env->mip;
}
@ -2988,7 +2979,7 @@ static RISCVException write_hgeie(CPURISCVState *env, int csrno,
val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
env->hgeie = val;
/* Update mip.SGEIP bit */
riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
riscv_cpu_update_mip(env, MIP_SGEIP,
BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
return RISCV_EXCP_NONE;
}
@ -3057,8 +3048,6 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@ -3069,8 +3058,8 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
env->htimedelta = val;
}
if (cpu->cfg.ext_sstc && env->rdtime_fn) {
riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
}
@ -3091,16 +3080,14 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
if (cpu->cfg.ext_sstc && env->rdtime_fn) {
riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
}

6
target/riscv/pmu.c
View File

@ -133,7 +133,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
/* Generate interrupt only if OF bit is clear */
if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
}
} else {
counter->mhpmcounterh_val++;
@ -172,7 +172,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
/* Generate interrupt only if OF bit is clear */
if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
}
} else {
counter->mhpmcounter_val++;
@ -371,7 +371,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,
/* Generate interrupt only if OF bit is clear */
if (!(*mhpmevent_val & of_bit_mask)) {
*mhpmevent_val |= of_bit_mask;
riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
}
}
}

15
target/riscv/time_helper.c
View File

@ -27,25 +27,24 @@ static void riscv_vstimer_cb(void *opaque)
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
env->vstime_irq = 1;
riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
}
static void riscv_stimer_cb(void *opaque)
{
RISCVCPU *cpu = opaque;
riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));
}
/*
* Called when timecmp is written to update the QEMU timer or immediately
* trigger timer interrupt if mtimecmp <= current timer value.
*/
void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
uint64_t timecmp, uint64_t delta,
uint32_t timer_irq)
{
uint64_t diff, ns_diff, next;
CPURISCVState *env = &cpu->env;
RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
uint32_t timebase_freq = mtimer->timebase_freq;
uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
@ -57,9 +56,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
*/
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 1;
riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
} else {
riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1));
}
return;
}
@ -67,9 +66,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
/* Clear the [VS|S]TIP bit in mip */
if (timer_irq == MIP_VSTIP) {
env->vstime_irq = 0;
riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
} else {
riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
}
/*

2
target/riscv/time_helper.h
View File

@ -22,7 +22,7 @@
#include "cpu.h"
#include "qemu/timer.h"
void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
uint64_t timecmp, uint64_t delta,
uint32_t timer_irq);
void riscv_timer_init(RISCVCPU *cpu);