LIU Zhiwei a60ce58fd9 target/riscv: Support Zama16b extension ... Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic. According to the specification, Zama16b applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions. Thus it should not apply to zacas or RVC instructions. For an instruction in that set, if all accessed bytes lie within 16B granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO—i.e., it will execute atomically. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240709113652.1239-6-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-07-18 12:00:42 +10:00
..
insn_trans	target/riscv: Support Zama16b extension	2024-07-18 12:00:42 +10:00
kvm	target/riscv/kvm: handle the exit with debug reason	2024-06-26 22:46:48 +10:00
tcg	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Reserve exception codes for sw-check and hw-err	2024-06-26 22:57:49 +10:00
cpu_cfg.h	target/riscv: Support Zama16b extension	2024-07-18 12:00:42 +10:00
cpu_helper.c	Misc HW & accelerators patch queue	2024-06-04 14:53:05 -05:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h
cpu.c	target/riscv: Support Zama16b extension	2024-07-18 12:00:42 +10:00
cpu.h	target/riscv: Introduce extension implied rules definition	2024-06-26 23:06:00 +10:00
crypto_helper.c
csr.c	target/riscv: fix instructions count handling in icount mode	2024-06-26 23:04:11 +10:00
debug.c	target/riscv: Apply modularized matching conditions for icount trigger	2024-06-27 13:09:16 +10:00
debug.h
fpu_helper.c	target/riscv: Fix froundnx.h nanbox check	2024-06-26 23:02:35 +10:00
gdbstub.c	riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()	2024-06-03 11:12:12 +10:00
helper.h	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
insn16.decode	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
insn32.decode	target/riscv: Add zimop extension	2024-07-18 12:00:42 +10:00
instmap.h
internals.h	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
Kconfig
m128_helper.c
machine.c
meson.build	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
monitor.c
op_helper.c	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
pmp.c
pmp.h
pmu.c
pmu.h
riscv-qmp-cmds.c
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	2024-06-03 11:12:11 +10:00
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
vcrypto_helper.c
vector_helper.c
vector_internals.c	target/riscv: Fix the element agnostic function problem	2024-06-03 11:12:12 +10:00
vector_internals.h
xthead.decode
XVentanaCondOps.decode
zce_helper.c