riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
Commit33a24910ae
changed 'reg_width' to use 'vlenb', i.e. vector length in bytes, when in this context we want 'reg_width' as the length in bits. Fix 'reg_width' back to the value in bits like7cb59921c0
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set beforehand. While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more clarity about what the variable represents. 'bitsize' is also used in riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to gdb_feature_builder_append_reg(). Cc: Akihiko Odaki <akihiko.odaki@daynix.com> Cc: Alex Bennée <alex.bennee@linaro.org> Reported-by: Robin Dapp <rdapp.gcc@gmail.com> Fixes:33a24910ae
("target/riscv: Use GDBFeature for dynamic XML") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Cc: qemu-stable <qemu-stable@nongnu.org> Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
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static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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int reg_width = cpu->cfg.vlenb;
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int bitsize = cpu->cfg.vlenb << 3;
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GDBFeatureBuilder builder;
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int i;
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@ -298,7 +298,7 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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int count = reg_width / vec_lanes[i].size;
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int count = bitsize / vec_lanes[i].size;
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gdb_feature_builder_append_tag(
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&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
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vec_lanes[i].id, vec_lanes[i].gdb_type, count);
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@ -316,7 +316,7 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
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/* Define vector registers */
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for (i = 0; i < 32; i++) {
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gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
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reg_width, i, "riscv_vector", "vector");
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bitsize, i, "riscv_vector", "vector");
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}
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gdb_feature_builder_end(&builder);
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