target/riscv: Reserve exception codes for sw-check and hw-err
Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-6-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -673,6 +673,8 @@ typedef enum RISCVException {
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RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
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RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
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RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
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RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */
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RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */
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RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
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RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
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RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
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