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9ea17007c4
qemu/target/riscv
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Ard Biesheuvel 9ea17007c4 target/riscv: Use existing lookup tables for MixColumns 
The AES MixColumns and InvMixColumns operations are relatively
expensive 4x4 matrix multiplications in GF(2^8), which is why C
implementations usually rely on precomputed lookup tables rather than
performing the calculations on demand.

Given that we already carry those tables in QEMU, we can just grab the
right value in the implementation of the RISC-V AES32 instructions. Note
that the tables in question are permuted according to the respective
Sbox, so we can omit the Sbox lookup as well in this case.

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Zewen Ye <lustrew@foxmail.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>
Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230731084043.1791984-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-11 11:45:54 +10:00
..
insn_trans riscv: spelling fixes 2023-09-08 13:08:52 +03:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h riscv: spelling fixes 2023-09-08 13:08:52 +03:00
cpu_cfg.h riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
cpu_helper.c target/riscv: Set the correct exception for implict G-stage translation fail 2023-07-10 22:29:15 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu-param.h target/riscv: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu.c target/riscv/cpu.c: add smepmp isa string 2023-09-11 11:45:54 +10:00
cpu.h riscv: spelling fixes 2023-09-08 13:08:52 +03:00
crypto_helper.c target/riscv: Use existing lookup tables for MixColumns 2023-09-11 11:45:54 +10:00
csr.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
debug.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
gdbstub.c target/riscv: Use PRV_RESERVED instead of PRV_H 2023-05-05 10:49:50 +10:00
helper.h riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Introduce mmuidx_2stage 2023-05-05 10:49:50 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_riscv.h target/riscv: use KVM scratch CPUs to init KVM properties 2023-07-10 22:29:15 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c kvm: Introduce kvm_arch_get_default_type hook 2023-08-22 17:31:02 +01:00
m128_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
machine.c target/riscv: Restrict KVM-specific fields from ArchCPU 2023-06-28 14:27:59 +02:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
monitor.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
op_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
pmp.c target/riscv: Smepmp: Return error when access permission not allowed in PMP 2023-06-13 17:45:30 +10:00
pmp.h target/riscv: Change the return type of pmp_hart_has_privs() to bool 2023-06-13 17:09:13 +10:00
pmu.c target/riscv/pmu: Restrict 'qemu/log.h' include to source 2023-08-31 19:47:43 +02:00
pmu.h target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c target/riscv: add TYPE_RISCV_DYNAMIC_CPU 2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
vector_helper.c target/riscv: Fix page_check_range use in fault-only-first 2023-09-11 11:45:54 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00