mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
80b605056d
qemu/target/riscv
History
Chao Du 80b605056d target/riscv/kvm: add software breakpoints support 
This patch implements insert/remove software breakpoint process.

For RISC-V, GDB treats single-step similarly to breakpoint: add a
breakpoint at the next step address, then continue. So this also
works for single-step debugging.

Implement kvm_arch_update_guest_debug(): Set the control flag
when there are active breakpoints. This will help KVM to know
the status in the userspace.

Add some stubs which are necessary for building, and will be
implemented later.

Signed-off-by: Chao Du <duchao@eswincomputing.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606014501.20763-2-duchao@eswincomputing.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26 22:45:14 +10:00
..
insn_trans target/riscv: rvzicbo: Fixup CBO extension register calculation 2024-06-03 11:12:12 +10:00
kvm target/riscv/kvm: add software breakpoints support 2024-06-26 22:45:14 +10:00
tcg target/riscv: zvbb implies zvkb 2024-06-26 22:30:52 +10:00
arch_dump.c target/riscv: Fix format for comments 2023-05-05 10:49:50 +10:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h target/riscv: Move Guest irqs out of the core local irqs range. 2024-06-26 22:29:17 +10:00
cpu_cfg.h target/riscv: Add support for Zve64x extension 2024-06-03 11:12:12 +10:00
cpu_helper.c Misc HW & accelerators patch queue 2024-06-04 14:53:05 -05:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
cpu-param.h target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h' 2024-04-26 15:31:37 +02:00
cpu-qom.h target/riscv: add rv32i, rv32e and rv64e CPUs 2024-02-09 20:49:41 +10:00
cpu.c Misc HW & accelerators patch queue 2024-06-04 14:53:05 -05:00
cpu.h Misc HW & accelerators patch queue 2024-06-04 14:53:05 -05:00
crypto_helper.c target/riscv: Use accelerated helper for AES64KS1I 2023-09-11 11:45:55 +10:00
csr.c target/riscv: Move Guest irqs out of the core local irqs range. 2024-06-26 22:29:17 +10:00
debug.c target/riscv/debug: set tval=pc in breakpoint exceptions 2024-06-03 11:12:12 +10:00
debug.h exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header 2024-04-26 17:03:05 +02:00
fpu_helper.c riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
gdbstub.c riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() 2024-06-03 11:12:12 +10:00
helper.h target/riscv: Raise exceptions on wrs.nto 2024-06-03 11:12:11 +10:00
insn16.decode target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00
insn32.decode target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Use env_archcpu() in [check_]nanbox() 2023-11-07 12:13:27 +01:00
Kconfig kconfig: express dependency of individual boards on libfdt 2024-05-10 15:45:15 +02:00
m128_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
machine.c target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit 2024-03-08 20:48:03 +10:00
meson.build riscv: thead: Add th.sxstatus CSR emulation 2024-06-03 11:12:12 +10:00
monitor.c riscv: spelling fixes 2023-09-08 13:08:52 +03:00
op_helper.c target/riscv: Raise exceptions on wrs.nto 2024-06-03 11:12:11 +10:00
pmp.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
pmp.h target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 2024-01-10 18:47:46 +10:00
pmu.c target/riscv: Add "pmu-mask" property to replace "pmu-num" 2023-11-07 11:06:02 +10:00
pmu.h target/riscv: Add missing include guard in pmu.h 2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c target: Improve error reporting for CpuModelInfo member @props 2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h target/riscv/kvm: implement SBI debug console (DBCN) calls 2024-06-03 11:12:11 +10:00
th_csr.c riscv: thead: Add th.sxstatus CSR emulation 2024-06-03 11:12:12 +10:00
time_helper.c target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c Misc HW & accelerators patch queue 2024-06-04 14:53:05 -05:00
vcrypto_helper.c target/riscv/vector_helpers: do early exit when vstart >= vl 2024-03-22 15:20:02 +10:00
vector_helper.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
vector_internals.c target/riscv: Fix the element agnostic function problem 2024-06-03 11:12:12 +10:00
vector_internals.h target/riscv/vector_helpers: do early exit when vstart >= vl 2024-03-22 15:20:02 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00