Commit Graph

117 Commits

Author SHA1 Message Date
aurel32
eeda67786c target-sh4: Add SH bit handling to TLB
This patch adds SH bit handling to sh4's TLB, which is a part of MMU
functionality that had not been implemented in qemu.

Additionally, increment_urc() call in cpu_load_tlb() is deleted, because
the specification explicitly says that URC is not incremented by an LDTLB
instruction (at Section 3 of SH7751 Hardware manual(REJ09B0370-0400)).
Even though URC is not needed to be strictly same as HW because it is a
random number, this condition is not negligible.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5971 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 17:31:51 +00:00
aurel32
f619837153 target-sh4: check FD bit for FP instructions
Based on a patch from Vladimir Prus <vladimir@codesourcery.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5970 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 17:31:43 +00:00
aurel32
b79e175259 SH4: kill a few warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 22:46:42 +00:00
aurel32
d8299bccf2 SH4: Implement FD bit
SH4 manual say that if a floating point instruction is executed while
FD bit in the status register is 1, an exception should be raised. QEMU
presently does not do that, so the kernel does not initialize FP state
for any thread, nor does it save/restore FP state. The most apparent
consequence is that while recent gcc/libc expect double-precision mode
to be set by kernel, they run in single-precision mode, and all FP code
produces wrong values.

This patch fixes this. It also fixes a couple of places where PC was
not updated before handling an exception, although both those places
deal with invalid instruction and don't lead to any user-visible bugs.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5937 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 22:46:31 +00:00
balrog
5c16736a37 SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).
Main purpose of this is to delete
       *physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers.
But, IMHO, it is logically wrong.

Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have
one more address called A7 which is usually P4 address with upper 3bits masked.
This is an address only appears in TLB's physical address part.

Current code use trick writing drivers as if they are really in A7
(that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:39:58 +00:00
balrog
1e5459a3fa SH: On-chip PCI controller support (Takashi YOSHII).
This patch adds SuperH on-chip PCI controller(PCIC) support.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:08:45 +00:00
aurel32
db8d990204 Remove FORCE_RET() and RETURN()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 18:15:54 +00:00
aurel32
2cbd949d7a Common cpu_loop_exit prototype
All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5820 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-30 16:23:09 +00:00
aliguori
c0ce998e94 Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25 22:13:57 +00:00
aurel32
11bb09f1be target-sh4: fix 64-bit fmov to/from memory
When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5773 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-22 10:09:27 +00:00
aurel32
cf7055bdfb target-sh4: fix TLB/MMU emulation
Based on a patch from Vladimir Prus and comments from Shin-ichiro KAWASAKI.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5770 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-21 22:33:15 +00:00
aurel32
12d961385b target-sh4: fix fldi0/fldi1
fldi0/fldi1 should be executed as a nop if FPSCR.FR is set instead of
generating an exception. Reported by Laurent Desnogues.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5759 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-20 06:41:29 +00:00
aurel32
66ba317c90 target-sh4: map FP registers as TCG variables
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5758 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19 18:00:47 +00:00
aurel32
9850d1e82c target-sh4: use CPU_Float/CPU_Double instead of ugly casts
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5757 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19 18:00:39 +00:00
aliguori
a1d1bb3101 Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists.
This also allows to return a stable reference to the related objects,
required for later introduced x86 debug register support.

Breakpoints and watchpoints are stored with their full information set
and an additional flag field that makes them easily extensible for use
beyond pure guest debugging.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 20:07:32 +00:00
aliguori
6b9175478e Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:46:41 +00:00
aliguori
622ed3605b Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:36:03 +00:00
pbrook
a7812ae412 TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 14:43:54 +00:00
blueswir1
b1d8e52e63 Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-26 13:43:07 +00:00
aurel32
7526aa2d00 SH4: Implement MOVUA.L
* target-sh4/translate.c (_decode_opc): Implement
   MOVUA.L.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5473 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-12 23:32:59 +00:00
aurel32
bdbf22e6b7 SH4: fix single-stepping
* target-sh/translate.c (gen_intermediate_code_internal): If
  singlestep is enabled, update PC before stopping.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5472 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-12 23:32:48 +00:00
aurel32
c69e3264c3 SH4: Fix swap.b
The SH4 manual documents the swap.b instruction as follows:

        SWAP.B Rm,Rn
                Rm → swap lower 2 bytes → Rn

Current QEMU code, in addition to the above, also clears the high
16 bits. The immediate breakage I saw is that htonl function applied
to  netmask of 255.255.255.0 gives 0, which breaks all networking.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5471 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-12 23:32:40 +00:00
blueswir1
1ed1a78738 Silence some warnings about no value returned from non-void function
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5430 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-05 11:47:55 +00:00
pbrook
36aa55dcd9 Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21 13:48:32 +00:00
blueswir1
b55266b5a2 Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20 08:07:15 +00:00
aurel32
fe25591e7b SH4: Privilege check for instructions
This patch adds check for all SH4 instructions which are
executed only in privileged mode.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5224 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-15 08:49:15 +00:00
aurel32
0b6d3ae072 qemu sh4 nptl support
(Michael Trimarchi)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5223 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-15 07:43:43 +00:00
aurel32
7478757e1f sh4: doesn't set the cpu_model_str
Fix setting of cpu_model_str for sh4

(Michael Trimarchi)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5222 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-15 07:34:45 +00:00
aurel32
f24f381b2d SH4: sleep instruction bug fix
fix a bug on 'sleep' instruction, which have caused halt of idle task.
As i386 'hlt' instruction does, it should save PC before sleep.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5220 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-15 06:42:30 +00:00
aurel32
0fd3ca30c4 sh4: CPU versioning.
Trivial patch adding CPU listing and the ability to do per-subtype
CVR/PVR/PRR values. Presently SH7750R and SH7751R definitions are
provided, as these are the ones in present use in-tree.

The CVR value for SH7751R is intentionally restricted so the kernel
boots, though this will want to be switched to the proper CVR value
once system emulation has sufficiently stabilized.

This also makes it trivial to abstract subtype specific registers like
MMU_PTEA and to set up feature bits in line with the kernel probing for
things like conditionalizing FPU/DSP context.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5133 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 16:18:28 +00:00
aurel32
86e0abc767 SH4: fix a regression introduced in r5122
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5132 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 08:42:16 +00:00
aurel32
17b086f71b SH4: Remove dyngen leftovers
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5126 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01 22:12:14 +00:00
aurel32
7fdf924fdd SH4: final conversion to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5125 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01 22:12:06 +00:00
aurel32
cc4ba6a982 SH4: convert floating-point ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01 22:11:56 +00:00
aurel32
c55497ecb8 SH4: Remove most uses of cpu_T[0] and cpu_T[1]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5122 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01 13:09:21 +00:00
aurel32
7efbe24165 SH4: TCG optimisations
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5121 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01 13:09:14 +00:00
aurel32
69d6275b00 SH4: Convert remaining non-fp ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01 13:09:06 +00:00
aurel32
c047da1af4 SH4: Convert shift functions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5119 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 22:37:17 +00:00
aurel32
390af82166 SH4: convert control/status register load/store to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 22:07:52 +00:00
aurel32
fa4da1074c SH4: Convert memory loads/stores to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5117 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 22:07:44 +00:00
aurel32
6f06939b68 SH4: convert some more arithmetics ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 13:55:14 +00:00
aurel32
e6afc2f4b9 SH4: convert a few helpers to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 23:01:41 +00:00
aurel32
1000822b03 SH4: convert branch/jump instructions to TCG
(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5111 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 22:32:32 +00:00
aurel32
a46256129e SH4: convert simple compare instructions to TCG
(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5108 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 20:12:18 +00:00
aurel32
3a8a44c4a8 SH4: convert a few control or system register functions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5107 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 16:32:18 +00:00
aurel32
829337a687 SH4: Fix bugs introduce in r5099
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5106 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 16:08:38 +00:00
aurel32
5aa3b1eaf8 SH4: fix xtrct Rm,Rn (broken in r5103)
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5105 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 13:27:29 +00:00
aurel32
559dd74de8 SH4: convert logic and arithmetic ops to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5103 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 10:05:12 +00:00
aurel32
1e8864f75d SH4: use TCG variables for gregs
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5102 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 00:48:50 +00:00
aurel32
3bf73a4980 SH4: use uint32_t/i32 based types/ops
Use uint32_t/i32 based types/ops to stay consistent with previous dyngen
code. Thanks to Paul Brook for noticing that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5101 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-28 21:37:53 +00:00