SH4: use uint32_t/i32 based types/ops
Use uint32_t/i32 based types/ops to stay consistent with previous dyngen code. Thanks to Paul Brook for noticing that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5101 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
8f99cc6c3e
commit
3bf73a4980
@ -79,21 +79,21 @@ static void sh4_translate_init(void)
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}
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/* General purpose registers moves. */
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static inline void gen_movl_imm_rN(target_ulong arg, int reg)
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static inline void gen_movl_imm_rN(uint32_t arg, int reg)
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{
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TCGv tmp = tcg_const_tl(arg);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
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TCGv tmp = tcg_const_i32(arg);
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tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, gregs[reg]));
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tcg_temp_free(tmp);
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}
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static always_inline void gen_movl_T_rN (TCGv t, int reg)
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{
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tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
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tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
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}
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static always_inline void gen_movl_rN_T (TCGv t, int reg)
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{
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tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, gregs[reg]));
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, gregs[reg]));
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}
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#ifdef CONFIG_USER_ONLY
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@ -355,12 +355,12 @@ void _decode_opc(DisasContext * ctx)
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gen_movl_imm_rN(B7_0s, REG(B11_8));
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return;
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case 0x9000: /* mov.w @(disp,PC),Rn */
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tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
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tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
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gen_op_ldw_T0_T0(ctx);
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gen_movl_T_rN(cpu_T[0], REG(B11_8));
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return;
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case 0xd000: /* mov.l @(disp,PC),Rn */
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tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
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tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
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gen_op_ldl_T0_T0(ctx);
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gen_movl_T_rN(cpu_T[0], REG(B11_8));
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return;
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@ -585,30 +585,30 @@ void _decode_opc(DisasContext * ctx)
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return;
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case 0x600e: /* exts.b Rm,Rn */
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
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tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
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tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]);
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gen_movl_T_rN(cpu_T[0], REG(B11_8));
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return;
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case 0x600f: /* exts.w Rm,Rn */
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
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gen_movl_T_rN(cpu_T[0], REG(B11_8));
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return;
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case 0x600c: /* extu.b Rm,Rn */
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff);
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gen_movl_T_rN(cpu_T[0], REG(B11_8));
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return;
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case 0x600d: /* extu.w Rm,Rn */
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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gen_movl_T_rN(cpu_T[0], REG(B11_8));
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return;
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case 0x000f: /* mac.l @Rm+,@Rn+ */
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gen_movl_rN_T(cpu_T[0], REG(B11_8));
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gen_op_ldl_T0_T0(ctx);
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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gen_op_ldl_T0_T0(ctx);
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gen_op_macl_T0_T1();
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@ -618,7 +618,7 @@ void _decode_opc(DisasContext * ctx)
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case 0x400f: /* mac.w @Rm+,@Rn+ */
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gen_movl_rN_T(cpu_T[0], REG(B11_8));
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gen_op_ldl_T0_T0(ctx);
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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gen_op_ldl_T0_T0(ctx);
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gen_op_macw_T0_T1();
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@ -632,18 +632,18 @@ void _decode_opc(DisasContext * ctx)
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return;
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case 0x200f: /* muls.w Rm,Rn */
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]);
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gen_movl_rN_T(cpu_T[1], REG(B11_8));
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tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
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tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
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tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
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tcg_gen_ext16s_i32(cpu_T[1], cpu_T[1]);
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gen_op_mulsw_T0_T1();
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return;
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case 0x200e: /* mulu.w Rm,Rn */
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gen_movl_rN_T(cpu_T[0], REG(B7_4));
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xffff);
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gen_movl_rN_T(cpu_T[1], REG(B11_8));
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tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffff);
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tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0xffff);
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gen_op_muluw_T0_T1();
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return;
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case 0x600b: /* neg Rm,Rn */
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@ -843,7 +843,7 @@ void _decode_opc(DisasContext * ctx)
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case 0xcd00: /* and.b #imm,@(R0,GBR) */
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gen_movl_rN_T(cpu_T[0], REG(0));
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gen_op_addl_GBR_T0();
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_op_ldub_T0_T0(ctx);
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gen_op_and_imm_T0(B7_0);
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gen_op_stb_T0_T1(ctx);
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@ -895,21 +895,21 @@ void _decode_opc(DisasContext * ctx)
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case 0xc000: /* mov.b R0,@(disp,GBR) */
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gen_op_stc_gbr_T0();
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gen_op_addl_imm_T0(B7_0);
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_movl_rN_T(cpu_T[0], REG(0));
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gen_op_stb_T0_T1(ctx);
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return;
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case 0xc100: /* mov.w R0,@(disp,GBR) */
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gen_op_stc_gbr_T0();
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gen_op_addl_imm_T0(B7_0 * 2);
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_movl_rN_T(cpu_T[0], REG(0));
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gen_op_stw_T0_T1(ctx);
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return;
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case 0xc200: /* mov.l R0,@(disp,GBR) */
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gen_op_stc_gbr_T0();
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gen_op_addl_imm_T0(B7_0 * 4);
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_movl_rN_T(cpu_T[0], REG(0));
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gen_op_stl_T0_T1(ctx);
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return;
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@ -947,7 +947,7 @@ void _decode_opc(DisasContext * ctx)
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case 0xcf00: /* or.b #imm,@(R0,GBR) */
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gen_movl_rN_T(cpu_T[0], REG(0));
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gen_op_addl_GBR_T0();
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_op_ldub_T0_T0(ctx);
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gen_op_or_imm_T0(B7_0);
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gen_op_stb_T0_T1(ctx);
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@ -972,7 +972,7 @@ void _decode_opc(DisasContext * ctx)
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case 0xce00: /* xor.b #imm,@(R0,GBR) */
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gen_movl_rN_T(cpu_T[0], REG(0));
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gen_op_addl_GBR_T0();
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_op_ldub_T0_T0(ctx);
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gen_op_xor_imm_T0(B7_0);
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gen_op_stb_T0_T1(ctx);
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@ -1142,7 +1142,7 @@ void _decode_opc(DisasContext * ctx)
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return;
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case 0x401b: /* tas.b @Rn */
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gen_movl_rN_T(cpu_T[0], REG(B11_8));
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
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gen_op_ldub_T0_T0(ctx);
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gen_op_cmp_eq_imm_T0(0);
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gen_op_or_imm_T0(0x80);
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@ -1213,14 +1213,14 @@ void _decode_opc(DisasContext * ctx)
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break;
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case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
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if (!(ctx->fpscr & FPSCR_PR)) {
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tcg_gen_movi_tl(cpu_T[0], 0);
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tcg_gen_movi_i32(cpu_T[0], 0);
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gen_op_fmov_T0_frN(FREG(B11_8));
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return;
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}
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break;
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case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
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if (!(ctx->fpscr & FPSCR_PR)) {
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tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
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tcg_gen_movi_i32(cpu_T[0], 0x3f800000);
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gen_op_fmov_T0_frN(FREG(B11_8));
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return;
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}
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