Commit Graph

277 Commits

Author SHA1 Message Date
Johan Bengtsson
2af9ab7737 target-arm: Add support for PKHxx in thumb2
The PKHxx instructions were not recognized by the thumb2 decoder. The
solution provided in this changeset is identical to the arm-mode
implementation.

Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 12:01:44 +00:00
Stefan Weil
9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Chih-Min Chao
ed89a2f1b1 target-arm : fix thumb2 parallel add/sub opcode decoding
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:29 +02:00
Paul Brook
41ba834146 NEON vldN optimization
When combining multiple values as part of a NEON array load, do explcit
shift/or rather than using gen_bfi.  This voids redundant mask
operations.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-06-11 20:37:51 +01:00
Blue Swirl
22ed1d3478 arm: remove dead assignments, spotted by clang analyzer
Value stored is never read.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-25 19:31:06 +00:00
Juha Riihimäki
8e31209eea target-arm: fix neon vmon/vmvn with modified immediate
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com>
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:12:24 +02:00
Lars Munch
d996882703 target-arm: resource leak fixes for iwmmxt disassemble
This patch fixes few resource leaks in the iwmmxt disassemble.

Signed-off-by: Lars Munch <lars@segv.dk>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
Johan Bengtsson
bedd2912c8 target-arm: Fix handling of AL condition in IT instruction
Do not try to insert a conditional jump over next instruction when the
condition code is AL as this will trigger an internal error.

Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23 22:10:45 +01:00
Adam Lackorzynski
ea825eeefd target-arm: make RFE usable with any register
The rfe instruction can be used with any register, not just sp. Adjust the
condition check accordingly.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 12:01:29 +01:00
Adam Lackorzynski
a990f58fed target-arm: Fix missing 'return' in SRS handling.
There's a return missing in the srs handling which leads to srs always being
treated an an invalid op.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06 23:22:22 +01:00
Juha Riihimäki
30d11a2a01 target-arm: neon vshll instruction fix
implementation only widened the 32bit source vector elements into a
64bit destination vector but forgot to perform the actual shifting
operation.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:30:56 +01:00
Riku Voipio
79b0e534c0 target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN
The rounding/truncating options were inverted. truncating
was done when rounding was meant and vice verse.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:30:04 +01:00
Paul Brook
c5883be235 ARM CP15 tls fix
Fix temporary handling in cp15 tls register load/store.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-23 14:45:16 +00:00
Rabin Vincent
b8b45b68f8 target-arm: implement Thumb-2 exception return
Support the "subs pc, lr" Thumb-2 exception return instruction.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19 13:38:43 +00:00
Rabin Vincent
fa26df032e target-arm: fix thumb CPS
The Thumb CPS currently does not work correctly: CPSID touches more bits
than the instruction wants to, and CPSIE does nothing.  Fix it by
passing the correct mask (the "affect" bits) and value.

Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-19 13:38:32 +00:00
Riku Voipio
3f26c1227e target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled
with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
already checked in cp15_user_ok.

While at it, make the cp15.c13 Thread ID registers available only on
ARMv6K and newer.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-02-06 17:19:43 +01:00
Aurelien Jarno
502e64fe23 target-arm: fix strexd
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-24 00:18:23 +01:00
Paul Brook
426f5abcaa ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-22 21:35:13 +00:00
Paul Brook
600114988c ARM FP16 support
Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19 16:45:20 +00:00
Aurelien Jarno
f669df275c target-arm: use native tcg-ops for ror/bic/vorn
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:27 +01:00
Juha Riihimäki
ca9a32e4f3 target-arm: fix neon vsri, vshl and vsli ops
Shift by immediate value is incorrectly overwritten by a temporary
variable in the processing of NEON vsri, vshl and vsli instructions.
This patch has been revised to also include a fix for the special
case where the code would previously try to shift an integer value
over 31 bits left/right.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
71b3c3dea2 target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are defined
as subarchitecture specific and real functionality for any of the
other bits has not been implemented in QEMU. However, current code
allows modifying all bits in the VFP FPEXC register leading to
problems when guest code is writing 1's to the subarchitecture
specific bits and checking whether the bits stay up to verify the
existence of functionality which in fact does not exist in QEMU.
This patch has been revised to include the same behavior change in
the gdb register write function.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
8449623376 target-arm: add support for neon vld1.64/vst1.64 instructions
Add support for NEON vld1.64 and vst1.64 instructions. This patch is
revised to follow more closely the specification and raises
undefined exception if 64bit element size is used for vld2/vst2 or
vld4/vst4 instructions.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
2301db4916 target-arm: fix neon vshrn/vrshrn ops
In the existing code shift value is clobbered during the pass loop.
This patch changes the code so that it stores the intermediate
result in the target neon register directly and eliminates the need
to use a temporary to hold the intermediate value thus leaving the
shift value in the temporary variable intact. This is a new patch
in this version of the patch series.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
25aeb69b8d target-arm: fix incorrect temporary variable freeing
tmp4 and tmp5 temporary variables are allocated using tcg_const_i32
but incorrectly released using dead_tmp which will cause resource
leak tracking to report false leaks.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by:  Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-26 20:36:47 +01:00
Juha.Riihimaki@nokia.com
7b2919a0b4 target-arm: optimize thumb 32-bit multiply
Current implementation of thumb mul instruction is implemented as a
32x32->64 multiply which then uses only 32 least significant bits of
the result. Replace that with a simple 32x32->32 multiply.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:22:13 +02:00
Juha Riihimäki
b75263d653 target-arm: cleanup internal resource leaks
Revised patch for getting rid of tcg temporary variable leaks in
target-arm/translate.c. This version also includes the leak patch for
gen_set_cpsr macro, now converted as a static inline function, which I
sent earlier as a separate patch on top of this patch.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:11:43 +02:00
Aurelien Jarno
dcc65026c4 target-arm: fix bugs introduced by 1b2b1e547b
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 16:00:18 +02:00
Aurelien Jarno
98a463171b target-arm: fix bugs introduced by 3174f8e91f
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 15:53:28 +02:00
Filip Navara
747a651e8e target-arm: remove cpu_T for ARM once and for all
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:18 +02:00
Filip Navara
312eea9f99 target-arm: convert VFP not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
da6b5335d5 target-arm: convert disas_iwmmxt_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
3a554c0f20 target-arm: convert disas_dsp_insn not use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
1b2b1e547b target-arm: convert disas_neon_ls_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
dd8fbd787e target-arm: convert disas_neon_data_insn and helpers not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
3174f8e91f target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
396e467cb1 target-arm: replace thumb usage of cpu_T registers by proper register allocations
The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register
allocation.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
15bb4eac12 target-arm: fix TANDC and TORC instructions
Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
194576157a target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions.

Bugs in the gen_neon_unzip register load code were also fixed.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
a6445c52aa target-arm: convert gen_lookup_tb not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
2fbac54be0 target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
c67b6b719b target-arm: fix SRS/RFE instructions
The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers.

From: Hyeonsung Jang <hsjang@ok-labs.com>
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
217aff9c76 target-arm: remove unused gen_movl_T2_reg function
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
288eebe54f target-arm: remove useless line that sets register that is never used again
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
12edd4f269 target-arm: get rid of temporary variable cache
The temporary variable cache in no longer need since tcg_temp_free was introduced.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
155c3eacd2 target-arm: use tcg_global_mem_new_i32 to allocate registers
Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG
and host registers could be used to optimize the generated code.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Filip Navara
024589f182 Remove unused gen_bx_T0 function.
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-24 09:09:15 -05:00
Juha Riihimäki
21aeb3430c fix ARMv7 data processing instructions
ARMv7 defines a new behavior for ARM data processing instructions
compared to earlier architecture revisions; when the destination
register is R15, a Branch and Exchange operation is executed rather
than a simple Branch to the target address. This patch corrects the
behavior of the emulation for the aforementioned operations. To be
applied after applying the previous patch in this patch set.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-15 03:18:42 +01:00
Juha Riihimäki
e9bb4aa977 fix ARMv7 data processing instructions
Modernize parts of target-arm/translate.c in preparation for the
modifications in the subsequent patch in this patch set. This is done
in order to avoid writing new code to target-arm/translate.c that
would use deprecated methods and/or variables.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-15 02:48:18 +01:00
aurel32
1b530a6dfc Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05 20:08:59 +00:00
pbrook
cbbccffc7a Fix ARM quadword VDUP (core register).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-17 12:19:58 +00:00
aurel32
66896cb803 tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13 09:34:48 +00:00
aliguori
8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:36:53 +00:00
aliguori
93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15 22:34:14 +00:00
aurel32
fad6cb1a56 Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:05:52 +00:00
pbrook
fe1479c3ad Implement (very) basic Thumb2-EE support. This doesn't actually implement
EE state, just the associated system coprocessor registers.  It is sufficient
to keep OS setup and context switching code happy.

Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6104 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 13:18:36 +00:00
pbrook
644ad8066d Fix VFP fixed point conversion routines.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 13:02:08 +00:00
balrog
955a7dd5e8 ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the smmul
and smmla instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5913 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 14:18:02 +00:00
balrog
ded9d29547 ARM: fix usad8 and usada8 usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the usad8
and usada8 instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5912 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 14:03:27 +00:00
balrog
4cc633c38b Patch holes in ARM translation (Laurent Desnogues).
- gen_set_CF_bit31:  use the right value to set carry flag
 - shifter_out_im:  remove a spurious semi-colon
 - add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN
   size 2 case
 - sbfx, ubfx are v6t2 instructions

The correct cps user mode behaviour is unclear so it's left out from the
commit until ARM decides it.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5908 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 13:32:09 +00:00
balrog
aaf2d97dcb ARM: cosmetics (Laurent Desnogues).
- remove macros that are not used
  - remove disass structure is_mem field which value is never used
  - correct a typo in a comment.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5907 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 13:20:16 +00:00
aliguori
c0ce998e94 Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-25 22:13:57 +00:00
aliguori
bfa50bc263 Remove premature memop TB terminations (Jan Kiszka)
Now that we can properly restore the pc on watchpoint hits, there is no
more need for prematurely terminating TBs if watchpoints are present.
Remove all related bits.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5742 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 20:26:41 +00:00
aliguori
a1d1bb3101 Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists.
This also allows to return a stable reference to the related objects,
required for later introduced x86 debug register support.

Breakpoints and watchpoints are stored with their full information set
and an additional flag field that makes them easily extensible for use
beyond pure guest debugging.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 20:07:32 +00:00
pbrook
a7812ae412 TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 14:43:54 +00:00
pbrook
c9fb531ab2 VFP fnmsc negative zero fix.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5610 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-03 19:09:29 +00:00
blueswir1
b1d8e52e63 Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-26 13:43:07 +00:00
pbrook
a47f43d272 Additional exclusive load/store instruction are v6K, not v6T2.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5518 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-22 21:42:54 +00:00
pbrook
86753403b2 Fix ARMv6t2 strex instructions.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5517 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-22 20:35:54 +00:00
pbrook
3018f2598c Fix ARM NEON vdup and vtbl bugs.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5286 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-22 00:52:42 +00:00
pbrook
e4b3861d15 Fix neon encoding comment.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5285 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21 23:15:38 +00:00
pbrook
36aa55dcd9 Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21 13:48:32 +00:00
balrog
b40d0353b0 Fix QADD / QSUB decoding on ARM (Torbjörn Andersson).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5273 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20 03:18:07 +00:00
blueswir1
79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 09:51:20 +00:00
balrog
7997d92f2c ARM: fix CPS masks (Vincent Palatin).
According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19 10:34:35 +00:00
balrog
22478e79f2 Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).
helper.c
 - copy reference c0_c2 to runtime c0_c2 and not c0_c1

op_helper.c
 - remove old code (PARAM1, probably some left over from old dyngen)
   that broke do_[us]sat

translate.c
 - gen_smul_dual should sign-extend from 16 bit to 32 bit and not from
   8 to 32
 - disas_arm_insn:
   * smlalxy:  that was completely wrong;  now the addition is
     performed as for smlald
   * pkhtb:  optional ASR not taken into account (similar
   * to [us]sat)
   * pkhtb/pkhbt: tmp2 is dead
   * smlald, smlsld, smuad, smusd, smlad, smlsd: rd
   * and rn swapped


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4898 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19 10:12:22 +00:00
ths
2cfc5f17d3 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-18 18:01:29 +00:00
pbrook
d60bb01cbb Terminate TB immediately after v7-M exception return.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4868 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-11 00:27:19 +00:00
ths
551bd27f22 Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-03 17:57:36 +00:00
ths
06e80fc927 Silence compiler warning.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4839 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-03 16:40:06 +00:00
ths
bf20dc076b Spelling fixes, spotted by Stuart Brady.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4809 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30 17:22:19 +00:00
pbrook
a50f5b9186 Suppress bogus compiler warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4803 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 15:25:29 +00:00
pbrook
2e70f6efa8 Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 01:03:05 +00:00
balrog
a60de94777 Mark a dead_tmp as such in ARM msr.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4648 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-02 02:29:26 +00:00
pbrook
fbb4a2e371 Implement ARM magic kernel page and TLS register.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 00:20:44 +00:00
pbrook
cb63669a54 Fix ARM conditional branch bug.
Add tcg_gen_brcondi.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24 02:22:00 +00:00
balrog
4aa9aca4c2 Remove arm's local not_i32 tcg op now that there's one in tcg.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4475 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-17 18:15:04 +00:00
pbrook
390efc54fb Add TCG native negation op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-11 14:35:37 +00:00
pbrook
868314358e Add zero extension (pseudo-)ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-11 12:22:01 +00:00
aurel32
d2856f1ad4 Factorize code in translate.c
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-28 00:32:32 +00:00
balrog
601d70b9e5 Remove an unused field and fix some non-code typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-20 01:03:45 +00:00
balrog
66230e0dee Correct more ARM VFP 32/64 and signed/unsigned typos.
Fixes unreadable fonts in Maemo guest.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4221 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-20 00:58:01 +00:00
balrog
422ebf6979 Save the exact SWI return address in Thumb mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4217 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-16 23:17:02 +00:00
balrog
e22f8f39f3 Correctly restore pc after an exception occured in Thumb mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4211 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-14 19:14:06 +00:00
balrog
5b340b51fd Fix ARM VFP related segfaults.
The fconst change is partly a guess.
VFP_OP1 is still unused.
An ARMv6 target still won't boot.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4210 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-14 02:19:57 +00:00
balrog
6a0d8a1d23 Fix the offset in Thumb bl instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4204 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-13 13:25:31 +00:00
balrog
2637a3beb9 Set an unset label in ARM strex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4203 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-13 03:15:14 +00:00
balrog
72f1c62f7d Fix ARM and Thumb ldlex/stlex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4202 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-13 01:53:27 +00:00
balrog
6c95676b16 Store the right TCG temp (typo).
Stops ARMv6 target from segfaulting early.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-13 00:57:49 +00:00
pbrook
6fbe23d50e ARM N=Z=1 flag fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-01 17:19:11 +00:00
pbrook
e677137d99 ARM TCG conversion 15/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4152 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:49:05 +00:00
pbrook
ad69471ce5 ARM TCG conversion 14/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:48:30 +00:00
pbrook
8f8e3aa451 ARM TCG conversion 13/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4150 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:48:01 +00:00
pbrook
8984bd2e83 ARM TCG conversion 12/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4149 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:48 +00:00
pbrook
5e3f878ad6 ARM TCG conversion 11/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4148 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:34 +00:00
pbrook
4373f3ceeb ARM TCG conversion 10/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:19 +00:00
pbrook
b010980544 ARM TCG conversion 9/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:03 +00:00
pbrook
d9ba48308d ARM TCG conversion 8/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4145 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:46:50 +00:00
pbrook
6ddbc6e4cf ARM TCG conversion 7/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:46:33 +00:00
pbrook
3670669ce2 ARM TCG conversion 6/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4143 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:46:19 +00:00
pbrook
8f01245ee7 ARM TCG conversion 5/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4142 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:46:03 +00:00
pbrook
1497c961af ARM TCG conversion 4/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4141 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:45:50 +00:00
pbrook
9a119ff6c1 ARM TCG conversion 3/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4140 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:45:35 +00:00
pbrook
f51bbbfefe ARM TCG conversion 2/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4139 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:45:13 +00:00
pbrook
b26eefb68e ARM TCG conversion 1/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4138 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:44:26 +00:00
bellard
57fec1fee9 use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-01 10:50:11 +00:00
pbrook
e160c51ccd Fix msr_mask.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3584 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11 14:36:36 +00:00
pbrook
9ee6e8bb85 ARMv7 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11 00:04:49 +00:00
ths
3b46e62427 find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-17 08:09:54 +00:00
ths
5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16 21:08:06 +00:00
ths
ce62e5ba09 Fix tb->size mishandling, by Daniel Jacobowitz.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-11 10:04:58 +00:00
balrog
2e23213f26 Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162
2007-08-01 02:31:54 +00:00
pbrook
39524770b2 Fix "blx lr" (Lauro Venancio).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2979 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-11 18:59:35 +00:00
balrog
7a774c875b Use the same offset for all STR and STM instructions that store r15, as specified in ARM ARM (patch from Chris McNett).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2970 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-10 13:53:18 +00:00
balrog
a90b7318ba Implement power state changes (IDLE and SLEEP) for PXA.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2762 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-01 01:28:01 +00:00
balrog
18c9b56060 Implement iwMMXt instruction set for the PXA270 cpu.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2752 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-30 02:02:17 +00:00
balrog
c1713132e0 Core features of ARM XScale processors. Main PXA270 and PXA255 peripherals.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2749 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-30 01:26:42 +00:00
ths
687fa640d4 Random bug fixes from code inspection, by Wang Cheng Yeh.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2580 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-02 08:18:36 +00:00
pbrook
5fd46862e5 ARM register index+writeback fix (Lauro Ramos Venancio).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2481 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-17 01:43:01 +00:00
pbrook
6658ffb81e Watchpoint support (previous commit got eaten by Savannah server crash).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2479 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-16 23:58:11 +00:00
pbrook
18acad9250 ARM doubleword post-modify fix (Daniel Jacobowitz).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2424 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-14 20:17:03 +00:00
pbrook
a94a6abff4 Fix ARM VFP debugging dumps.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2201 c046a42c-6fe2-441c-8c8c-71466251a162
2006-10-25 17:43:33 +00:00
pbrook
191f9a93f4 ARM postincrememnt addressing fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1970 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-14 14:36:07 +00:00
bellard
159f366388 ARM undefined instruction execution (Jason Wessel)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1938 c046a42c-6fe2-441c-8c8c-71466251a162
2006-05-22 23:06:04 +00:00
pbrook
358bf29e80 Thumb prefetch abort fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1805 c046a42c-6fe2-441c-8c8c-71466251a162
2006-04-09 14:38:57 +00:00
pbrook
40f137e1ea Add Arm926 core support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1765 c046a42c-6fe2-441c-8c8c-71466251a162
2006-02-20 00:33:36 +00:00
pbrook
2ae23e7504 Fix Arm msr spsr bug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1761 c046a42c-6fe2-441c-8c8c-71466251a162
2006-02-11 16:20:39 +00:00
pbrook
3aa22b4b53 Fix Thumb variable shift condition code bug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1748 c046a42c-6fe2-441c-8c8c-71466251a162
2006-02-07 03:34:35 +00:00
pbrook
191abaa2f0 Fix Arm interrupted ldm bug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1743 c046a42c-6fe2-441c-8c8c-71466251a162
2006-02-04 21:50:36 +00:00
pbrook
06c949e62a Implement Arm BKPT instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1740 c046a42c-6fe2-441c-8c8c-71466251a162
2006-02-04 19:35:26 +00:00
bellard
68998c5de3 cpu_reset() fix (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1712 c046a42c-6fe2-441c-8c8c-71466251a162
2005-12-18 16:55:25 +00:00
bellard
ee0971849e Arm mulxy insn fix (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1683 c046a42c-6fe2-441c-8c8c-71466251a162
2005-12-04 18:56:28 +00:00
bellard
9332f9dafa ARM CPU suspend/halt (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1663 c046a42c-6fe2-441c-8c8c-71466251a162
2005-11-26 10:46:39 +00:00
bellard
b5ff1b3127 ARM system emulation (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1661 c046a42c-6fe2-441c-8c8c-71466251a162
2005-11-26 10:38:39 +00:00
bellard
173d6cfe51 cpu_exec_init() change
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1643 c046a42c-6fe2-441c-8c8c-71466251a162
2005-11-21 23:32:20 +00:00
bellard
6e256c935c use direct jump only for jumps in the same page
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1629 c046a42c-6fe2-441c-8c8c-71466251a162
2005-11-20 10:32:05 +00:00
bellard
2531fc7bc0 thumb BLX insn fix (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1607 c046a42c-6fe2-441c-8c8c-71466251a162
2005-11-06 19:36:29 +00:00
bellard
c53be33474 suppressed JUMP_TB (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1594 c046a42c-6fe2-441c-8c8c-71466251a162
2005-10-30 21:39:19 +00:00