Commit Graph

393 Commits

Author SHA1 Message Date
Evgeny Voevodin
efd7f48600 TCG: Use gen_opc_ptr from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-11-17 13:53:27 +00:00
Blue Swirl
f4359b9ffe disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Richard Henderson <rth@twiddle.net>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
2012-11-10 13:49:20 +00:00
Richard Henderson
e7d51b3450 target-sparc: Revert setting cpu_dst to gen_dest_gpr
There is some read-after-write error within the OP=2 insns which
prevents setting cpu_dst to the real output register.  Until this
is found and fixed, always write to a temporary first.

Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-30 18:52:04 +00:00
Aurelien Jarno
e7c8afb905 target-sparc: fix FMOVr instruction
Like the MOVr instruction, the FMOVr instruction has the condition
encoded between bits 10 and 12.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 09:02:38 +00:00
Richard Henderson
de9e9d9f17 target-sparc: Remove cpu_tmp0 as a global
Subroutines do their own local temporary management.
Within disas_sparc_insn we limit the existance of the variable
to OP=2 insns, and delay initialization as late as is reasonable
for the specific XOP.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
5793f2a47e target-sparc: Make cpu_dst local to OP=2 insns
And initialize it such that it (may) write directly to rd.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
7b04bd5cca target-sparc: Only use cpu_dst for eventual writes to a gpr
Use cpu_tmp0 for other stuff, like Write Priv Register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
abcc71919c target-sparc: Remove last uses of cpu_tmp64
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
aeff993cc5 target-sparc: Remove cpu_tmp64 use from softint insns
The use of "tl" functions and a tmp64 is logically incompatible.
Use cpu_tmp0 instead.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
3886b8a320 target-sparc: Don't use a temporary for gen_dest_fpr_D
In all cases we don't have write-before-read problems.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
1ec789ab68 target-sparc: Remove usage of cpu_tmp64 from most helper functions
Use a locally allocated temporary instead.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
f8641947c2 target-sparc: Tidy ldfsr, stfsr
Remove the last uses of cpu_tmp32.  Unify the code between sparc64
and sparc32 by using the proper "tl" functions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:07 +00:00
Richard Henderson
7b9e066b67 target-sparc: Avoid cpu_tmp32 in Write Priv Register
No need to copy to a temporary to store 32 bits.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
45778f99f0 target-sparc: Avoid cpu_tmp32 in Read Priv Register
We don't need another temporary here.  Load directly into the
register we want to set.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
ba5f5179f2 target-sparc: Use get_temp_i32 in gen_dest_fpr_F
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
2ae23e1782 target-sparc: Split out get_temp_i32
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
5e6ed43923 target-sparc: Make the cpu_addr variable local to load/store handling
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
a427352487 target-sparc: Cleanup cpu_src[12] allocation
Now that get_temp_tl is used for get_src[12], we don't need to
pre-allocate these temporaries.

Fallout from this is moving some assignments around cas/casx to
avoid uninitialized variable warnings.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
81634eea3d target-sparc: Finish conversion to gen_load_gpr
All users of gen_movl_{reg_TN,TN_reg} are removed.  At the same time,
make cpu_val a local variable for load/store disassembly.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
06828032e3 target-sparc: Convert swap to gen_load/store_gpr
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
c7785e1682 target-sparc: Convert asi helpers to gen_*_gpr
Push the DisasContext down so that we can use gen_load/store_gpr
in sode gen_ldda_asi, gen_stda_ast, gen_cas_asi, gen_casx_asi.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
9d1d4e342c target-sparc: Use gen_load_gpr in get_src[12]
This means we can avoid the incoming temporary, though the cleanup
of the existing temporaries is not performed in this patch.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
97ea285917 target-sparc: Conversion to gen_*_gpr, part 1
Only handle the easy cases directly within disas_sparc_insn.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
8802361689 target-sparc: Add gen_load/store/dest_gpr
Infrastructure to be used to clean up handling of temporaries.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:05 +00:00
Richard Henderson
20132b9605 target-sparc: Don't compute full flags value so often
Avoid speculatively computing flags before every potentially trapping
operation and instead do the flags computation when a trap actually
occurs.  This gives approximately 30% speedup in emulation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13 10:17:28 +00:00
Richard Henderson
6234ac09a9 target-sparc: Avoid unnecessary local temporaries
Now that save_state never ends a BB, we don't need to copy
values into local temps around it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13 10:17:28 +00:00
Richard Henderson
96b5a3d3cf target-sparc: Optimize CC_OP_LOGIC conditions
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13 10:17:28 +00:00
Richard Henderson
0fa2a0660c target-sparc: Fix optimized %icc comparisons
Signed-off-by: Richard Henderson <rth@twiddle.net>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13 10:17:28 +00:00
Richard Henderson
2a484ecf82 target-sparc: Optimize conditionals using SUBCC
Aka "normal" comparisons.  We now have the infrastructure to
pass back non-boolean results from gen_compare.  This will
automatically get used by both branches and conditional moves.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:34 +00:00
Richard Henderson
fe1755cbb2 target-sparc: Fall through from not-taken trap
Now that we've cleaned up global temporary allocation, we can
continue translating the fallthru path of a conditional trap.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:34 +00:00
Richard Henderson
b09b2fd30c target-sparc: Cleanup "global" temporary allocation
There are 6 temporaries that disas_sparc_insn relies on having been
allocated.  Now that they are no longer referenced across branches,
they need not be allocated as local temps.

Move the allocation/free of these temporaries to make it clear that
they are local to the translation of a single insn.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:34 +00:00
Richard Henderson
690995a615 target-sparc: Use movcond for FMOV*R
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:34 +00:00
Richard Henderson
6cb675b0f8 target-sparc: Use movcond in mulscc
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:33 +00:00
Richard Henderson
a2ea4aa989 target-sparc: Move taddcctv and tsubcctv out of line
The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.

Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:33 +00:00
Richard Henderson
bd49ed41eb target-sparc: Tidy Tcc
Share more code between unconditional and conditional paths.

Move the computation of the trap number into the conditional BB;
avoid using temporaries that have gone out of scope (cpu_tmp32)
or rely on local temps (cpu_dst).

Fully fold the exception number when the trap number is %g0+imm.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:33 +00:00
Richard Henderson
c28ae41ecd target-sparc: Move sdivx and udivx out of line
The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:33 +00:00
Richard Henderson
61316742e2 target-sparc: Use movcond in gen_generic_branch
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:32 +00:00
Richard Henderson
c33f80f52a target-sparc: Use DisasCompare and movcond in MOVR
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:32 +00:00
Richard Henderson
f52879b441 target-sparc: Use DisasCompare and movcond in MOVCC
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:32 +00:00
Richard Henderson
7e480893cc target-sparc: Use DisasCompare and movcond in FMOVR, FMOVCC
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:32 +00:00
Richard Henderson
3a49e7598b target-sparc: Use DisasCompare in Tcc
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
416fcaea1e target-sparc: Introduce DisasCompare and functions to generate it
For the moment gen_cond et al retain their existing interface,
using setcond to turn a (potential) comparison back into a boolean.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
2e655fe768 target-sparc: Tidy gen_generic_branch interface
The arguments passed are always the same.
Pass down just DisasContext instead.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
934da7ee08 target-sparc: Tidy save_npc interface
Use the cpu_cond global register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:31 +00:00
Richard Henderson
13a6dd0043 target-sparc: Tidy gen_mov_pc_npc interface
Use the cpu_cond global register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
66442b07ae target-sparc: Tidy save_state interface
Use the cpu_cond global register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
5b12f1e8a1 target-sparc: Tidy gen_trap_ifnofpu interface
We always pass cpu_cond to the cond parameter.  Use that global
register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
dee8913cbf target-sparc: Tidy flush_cond interface
We always pass cpu_cond to the cond parameter.  Use that global
register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:30 +00:00
Richard Henderson
d4a288ef9c target-sparc: Tidy do_branch interfaces
We always pass cpu_cond to the r_cond parameter.  Use that global
register directly instead of passing it down.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07 16:39:29 +00:00
Richard Henderson
fdefe51c28 Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-27 21:38:50 +02:00
Artyom Tarasenko
22036a49dd Implement address masking for SPARC v9 CPUs
According to UltraSPARC - IIi User's manual:

14.1.11 Address Masking (Impdep #125)
When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps
transmit zero in the high-order 32-bits of the PC to their specified
destination registers.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-05-12 09:46:00 +00:00
Blue Swirl
0184e266cb Sparc: avoid AREG0 wrappers for memory access helpers
Adjust generation of load and store templates so that the functions
take a parameter for CPUState instead of relying on global env.

Remove wrappers. Move remaining memory helpers to ldst_helper.c.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:22:02 +00:00
Blue Swirl
fe8d8f0f1c Sparc: avoid AREG0 for memory access helpers
Make memory access helpers take a parameter for CPUState instead
of relying on global env. Introduce wrappers for load and store ops.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:22:00 +00:00
Andreas Färber
c5f9864e89 target-sparc: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc]
  sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:25 +01:00
Fabien Chouteau
96d922a654 Improve "ta 0" shutdown
This patch replace the previous implementation with this simplified and
more complete version (no shutdown when psret == 1).

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-19 11:22:57 +00:00
Richard Henderson
50c796f9d8 target-sparc: Implement FALIGNDATA inline.
This is a relatively simple sequence of shifts.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
793a137a41 target-sparc: Implement BMASK/BSHUFFLE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
add545ab11 target-sparc: Implement ALIGNADDR* inline.
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not
implemeneted at all.  However, this is a very simple operation
so we're better off doing this inline.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
6c07355325 target-sparc: Implement EDGE* instructions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:19 -07:00
Richard Henderson
2dedf31497 target-sparc: Implement fpack{16,32,fix}.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 14:00:17 -07:00
Richard Henderson
f888300b81 target-sparc: Implement PDIST.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:58:48 -07:00
Richard Henderson
445167723d target-sparc: Do exceptions management fully inside the helpers.
This reduces the size of the individual translation blocks, since
we only emit a single call for each FOP rather than three.  In
addition, clear_float_exceptions expands inline to a single byte store.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:57:06 -07:00
Richard Henderson
30038fd818 target-sparc: Change fpr representation to doubles.
This allows a more efficient representation for 64-bit hosts.
It should be about the same for 32-bit hosts, as we can still
access the individual pieces of the double.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:26 -07:00
Richard Henderson
45c7b743cd target-sparc: Undo cpu_fpr rename.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:26 -07:00
Richard Henderson
ac11f7767f target-sparc: Extract float128 move to a function.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:26 -07:00
Richard Henderson
61f17f6eba target-sparc: Extract common code for floating-point operations.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:55:24 -07:00
Richard Henderson
f027c3b192 target-sparc: Make FPU/VIS helpers const when possible.
This also removes the unused ENV parameter from these helpers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
03fb8cfc63 target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
96eda02412 target-sparc: Add accessors for double-precision fpr access.
Begin using i64 quantities to manipulate double-precision values.
On a 64-bit host this will, for the moment, generate less efficient
code; on a 32-bit host code quality should be largely unchanged.
Code quality for 64-bit will be adjusted with a subsequent patch.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
141ae5c13f target-sparc: Mark fprs dirty in store accessor.
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:45 -07:00
Richard Henderson
208ae65722 target-sparc: Add accessors for single-precision fpr access.
Load, store, and "create destination".  This version attempts to
change the behaviour of the translator as little as possible.  We
previously used cpu_tmp32 as the temporary destination, and we
continue to use that.  This will eventually allow a change in
representation of the fprs.

Change the name of the cpu_fpr array to make certain that all
instances are converted.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26 13:50:42 -07:00
Blue Swirl
7a5e4488cd Sparc: avoid AREG0 for division op helpers
Make [su]div{,cc} helpers take a parameter for CPUState instead
of relying on global env. Move the functions to helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:52 +00:00
Blue Swirl
7922703623 Sparc: avoid AREG0 for softint op helpers and Leon cache control
Make softint op helpers and Leon cache irq manager take a parameter
for CPUState instead of relying on global env. Move the functions
to int{32,64}_helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:09 +00:00
Blue Swirl
063c367558 Sparc: avoid AREG0 for CWP and PSTATE helpers
Make CWP and PSTATE helpers take a parameter for CPUState instead
of relying on global env. Remove wrapper functions.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26 17:18:04 +00:00
Stefan Weil
f37e2a6bb3 target-sparc: Fix order of function parameters
The MinGW-w64 gcc complains about wrong parameters for
gen_helper_fpadd16_s and three other functions.

gen_helper_fpadd16_s is declared like this (hidden in lots of macros):

static inline void
 gen_helper_fpadd16s(TCGv_i32 retval, TCGv_ptr arg1,
                     TCGv_i32 arg2, TCGv_i32 arg3);

So it looks like cpu_env should be the 2nd parameter.

Please review this patch as I have no environment to test it
(maybe the 1st parameter should be cpu_dst?).

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-25 19:30:00 +00:00
Blue Swirl
2ffd9176b1 Sparc: avoid AREG0 for lazy condition code helpers
Make lazy condition code helpers take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:09:37 +00:00
Blue Swirl
2e2f4ade86 Sparc: avoid AREG0 for float and VIS ops
Make floating point and VIS ops take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:09:13 +00:00
Blue Swirl
bc2653195a Sparc: avoid AREG0 for raise_exception and helper_debug
Make raise_exception() and helper_debug() take a parameter for
CPUState instead of relying on global env. Move the functions
to helper.c.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23 15:08:22 +00:00
Artyom Tarasenko
548f66db33 Fix handling of conditional branches in delay slot of a conditional branch
Check whether dc->npc is dynamic before using its value for branch.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-06 15:08:31 +00:00
Tsuneo Saito
638737ad03 SPARC64: implement %fprs dirty bits
Implement %fprs.DU/DL bits.
The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31
and %f32-63 respectively.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 08:26:45 +00:00
Tsuneo Saito
ccb57e0ea7 SPARC64: fix fnor* and fnand*
Fix the problem that result values are not assigned to the destination
registers.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 08:26:45 +00:00
Tsuneo Saito
b7d69dc233 SPARC64: add missing break on fmovdcc
"break" is missing on V9 fmovdcc (%icc).

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 20:44:50 +00:00
Tsuneo Saito
afcb737512 SPARC64: fix VIS1 SIMD signed compare instructions
The destination registers of SIMD signed compare instructions
(fcmp*<16|32>) are not FP registers but general purpose r registers.
Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 20:44:23 +00:00
Blue Swirl
f838e2c535 Sparc: fix FPU and AM enable checks for translation
Translation used incorrectly CPUState fields directly to check
for FPU enable state and 32 bit address masking on Sparc64.

Fix by using TB flags instead.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 17:30:43 +00:00
Tsuneo Saito
5f06b54718 SPARC64: fp_disabled checks on stfa/stdfa/stqfa
stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 15:36:15 +00:00
Tsuneo Saito
e1ef36c4a3 SPARC64: Implement stfa/stdfa/stqfa instrcutions properly
This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 15:36:10 +00:00
Tsuneo Saito
8872eb4f56 SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-14 15:35:01 +00:00
Artyom Tarasenko
8e91ed3080 fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivx
udivx and sdvix don't modify condition flags, so they shall not
overwrite cpu_cc_*

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 21:28:00 +00:00
Blue Swirl
2b41f10e18 Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:35 +00:00
Blue Swirl
dcfd14b374 Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate an
area of a TB which the guest explicitly flushes from i-cache. However,
QEMU detects writes to code areas where TBs have been generated, so
his has never been useful.

Delete the function, adjust callers.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-22 10:47:28 +00:00
Blue Swirl
86f1f2aee8 sparc64: fix incorrect BPcc target sign extension
Fix wrong number of bits used when sign extending the branch offset of BPcc
instructions.

Reported-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-14 07:30:31 +00:00
Blue Swirl
a2589e5cf2 sparc64: fix wrpstate and wrtl on delay slot
Use TCG local to work around TCG register flush due to a branch.

Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-14 07:30:28 +00:00
Stefan Weil
e87b7cb0f0 Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commit
d2856f1ad4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c.

Parameter puc was needed by target-sparc until
commit d7da2a1040.

Remove searched_pc from the debug statement and remove both
parameters from the parameter list of gen_pc_load.

As the function name gen_pc_load was also misleading,
it is now called restore_state_to_opc. This new name
was suggested by Peter Maydell, thanks.

v2: Remove last parameter, too, and rename the function.

v3: Fix [] typo in target-arm/translate.c.
    Fix wrong SHA1 object name in commit message (copy+paste error).

Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20 10:33:59 +02:00
Stefan Weil
4b4a72e556 Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).

These changes are needed for build environments where
sizeof(long) != sizeof(void *), especially for w64.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10 00:45:16 +02:00
Fabien Chouteau
4a2ba23284 SPARC: Add asr17 register support
This register is activated by CPU_FEATURE_ASR17 in the feature field.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-24 20:54:34 +00:00
Fabien Chouteau
b04d989054 SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more
information on http://www.gaisler.com).

Leon3 is made of multiple components available in the GrLib VHDL library.
Three devices are implemented: uart, timers and IRQ manager.
You can find code for these peripherals in the grlib_* files.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-24 20:54:34 +00:00
Aurelien Jarno
0fcec41eec target-sparc: fix udiv(cc) and sdiv(cc)
Since commit 5a4bb580cd, Xorg crashes on
a Debian Etch image. The commit itself is fine, but it triggers a bug
due to wrong computation of flags for udiv(cc) and sdiv(cc).

This patch only compute cc_src2 for the cc version of udiv/sdiv. It
also moves the update of cc_dst and cc_op to the helper, as it is
faster doing it here when there is already an helper.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-28 18:44:51 +00:00
Igor V. Kovalenko
fb170183e7 sparc64: fix umul and smul insns
- truncate and sign or zero extend operands before multiplication
- factor out common code to gen_op_multiply() with parameter to sign/zero extend
- call gen_op_multiply from gen_op_umul and gen_op_smul

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-02 20:08:44 +00:00
Igor V. Kovalenko
fe987e2394 sparc64: fix ldxfsr insn
- rearrange code to break from switch when appropriate
- allow deprecated ldfsr insn

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-02 20:05:30 +00:00
Igor V. Kovalenko
1295001c53 sparc64: fix missing address masking v1
- address masking for ldqf and stqf insns
- address masking for lddf and stdf insns
- address masking for translating ASI (Ultrasparc IIi)
v0->v1:
- move arch-specific code to helpers and drop more ifdefs at call sites
  using new helper asi_address_mask()
- change user emulation to use asi_address_mask()

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-02 20:03:52 +00:00