Commit Graph

108849 Commits

Author SHA1 Message Date
Richard Henderson
84e224d422 target/hppa: Decode d for bb instructions
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
63c427c615 target/hppa: Decode d for sub instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
faf97ba157 target/hppa: Decode d for add instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
345aa35f15 target/hppa: Decode d for cmpclr instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
af24075333 target/hppa: Decode d for unit instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
fa8e3bed38 target/hppa: Decode d for logical instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
08db178544 target/hppa: Remove TARGET_HPPA64
Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
e207b4aa71 target/hppa: Drop attempted gdbstub support for hppa64
There is no support for hppa64 in gdb.  Any attempt to provide the
data for the larger hppa64 registers results in an error from gdb.
Mask CR_SAR writes to the width of the register: 5 or 6 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
0c01f9ba2d linux-user/hppa: Fixes for TARGET_ABI32
Avoid target_ulong and use abi_* types.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:34 -08:00
Richard Henderson
59963d8fdf target/hppa: Pass d to do_unit_cond
Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
4fa52edf91 target/hppa: Pass d to do_sed_cond
Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
b5af84233d target/hppa: Pass d to do_log_cond
Hoist the resolution of d up one level above do_log_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
4fe9533acc target/hppa: Pass d to do_sub_cond
Hoist the resolution of d up one level above do_sub_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
a751eb31b6 target/hppa: Pass d to do_cond
Hoist the resolution of d up one level above do_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Helge Deller
f3618f59f3 target/hppa: sar register allows only 5 bits on 32-bit CPU
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06 18:49:33 -08:00
Richard Henderson
f13bf343cc target/hppa: Mask inputs in copy_iaoq_entry
Ensure that the destination is always a valid GVA offset.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
9a91dd8452 target/hppa: Use copy_iaoq_entry for link in do_ibranch
We need to make sure the link is masked properly along the
use_nullify_skip path.  The other three settings of a link
register already use this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
a01809737e target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]
This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.

Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
741322f471 target/hppa: Pass DisasContext to copy_iaoq_entry
Interface change only, no functional effect.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
698240d19b target/hppa: Fix hppa64 addressing
In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
5718fe4cfe target/hppa: Adjust hppa_cpu_dump_state for hppa64
Dump all 64 bits for pa2.0 and low 32 bits for pa1.x.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
ccdf741c48 target/hppa: Handle absolute addresses for pa2.0
With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
931adff314 target/hppa: Update cpu_hppa_get/put_psw for hppa64
With 64-bit registers, there are 16 carry bits in the PSW.
Clear reserved bits based on cpu revision.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
ca4c2008f5 target/hppa: Implement hppa_cpu_class_by_name
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
d3ae32d4d2 target/hppa: Implement cpu_list
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
9cf2112be4 target/hppa: Make HPPA_BTLB_ENTRIES variable
Depend on hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
bd6243a33f target/hppa: Introduce TYPE_HPPA64_CPU
Prepare for the qemu binary supporting both pa10 and pa20
at the same time.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
d781cb7798 target/hppa: Fix extrw and depw with sar for hppa64
These are 32-bit operations regardless of processor.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
1e9ab9fbe0 target/hppa: Fix bb_sar for hppa64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
bdcccc17ac target/hppa: Fix do_add, do_sub for hppa64
Select the proper carry bit for input to the arithmetic
and for output for the condition.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
72ca87535e target/hppa: Fix trans_ds for hppa64
This instruction always uses the input carry from bit 32,
but produces all 16 output carry bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
e1d635e871 target/hppa: Truncate rotate count in trans_shrpw_sar
When forcing rotate by i32, the shift count must be as well.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
c1f55d9795 target/hppa: Fix load in do_load_32
The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32
not tcg_gen_qemu_ld_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
0238e678eb target/hppa: Fix hppa64 case in machine.c
Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
d4e5803316 target/hppa: Remove load_const
Replace with tcg_constant_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
a6779861fd target/hppa: Remove get_temp_tl
Replace with tcg_temp_new_tl without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
e12c63090b target/hppa: Remove get_temp
Replace with tcg_temp_new without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
d7553f3591 target/hppa: Populate an interval tree with valid tlb entries
Complete the data structure conversion started earlier.  This reduces
the perf overhead of hppa_get_physical_address from ~5% to ~0.25%.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
09cae8255f target/hppa: Split out hppa_flush_tlb_range
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
f8cda28b8d target/hppa: Always report one page to tlb_set_page
No need to trigger the large_page_mask code unnecessarily.
Drop the now unused HPPATLBEntry.page_size field.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
66866cc74f target/hppa: Use IntervalTreeNode in HPPATLBEntry
Replace the va_b and va_b fields with the interval tree node.
The actual interval tree is not yet used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
729cd3506d target/hppa: Rename hppa_tlb_entry to HPPATLBEntry
Rename to CamelCase per coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Richard Henderson
bb67ec32a0 target/hppa: Include PSW_P in tb flags and mmu index
Use a separate mmu index for PSW_P enabled vs disabled.
This means we can elide the tlb flush in cpu_hppa_put_psw
when PSW_P changes.  This turns out to be the majority
of all tlb flushes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06 18:49:33 -08:00
Stefan Hajnoczi
80aaef96b1 Block patches:
- One patch to make qcow2's discard-no-unref option do better what it is
   supposed to do (i.e. prevent fragmentation)
 - Two fixes for zoned requests
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Merge tag 'pull-block-2023-11-06' of https://gitlab.com/hreitz/qemu into staging

Block patches:
- One patch to make qcow2's discard-no-unref option do better what it is
  supposed to do (i.e. prevent fragmentation)
- Two fixes for zoned requests

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# gpg: Signature made Tue 07 Nov 2023 01:09:12 HKT
# gpg:                using RSA key CB62D7A0EE3829E45F004D34A1FA40D098019CDF
# gpg:                issuer "hreitz@redhat.com"
# gpg: Good signature from "Hanna Reitz <hreitz@redhat.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CB62 D7A0 EE38 29E4 5F00  4D34 A1FA 40D0 9801 9CDF

* tag 'pull-block-2023-11-06' of https://gitlab.com/hreitz/qemu:
  file-posix: fix over-writing of returning zone_append offset
  block/file-posix: fix update_zones_wp() caller
  qcow2: keep reference on zeroize with discard-no-unref enabled

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07 09:42:18 +08:00
Stefan Hajnoczi
f6b174ff96 target-arm queue:
* hw/arm/virt: fix PMU IRQ registration
  * hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables
  * hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
  * util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
  * mc146818rtc: rtc_set_time(): initialize tm to zeroes
  * block/nvme: nvme_process_completion() fix bound for cid
  * hw/core/loader: gunzip(): initialize z_stream
  * io/channel-socket: qio_channel_socket_flush(): improve msg validation
  * hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
  * target/arm: Fix A64 LDRA immediate decode
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Merge tag 'pull-target-arm-20231106' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/arm/virt: fix PMU IRQ registration
 * hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables
 * hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
 * util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
 * mc146818rtc: rtc_set_time(): initialize tm to zeroes
 * block/nvme: nvme_process_completion() fix bound for cid
 * hw/core/loader: gunzip(): initialize z_stream
 * io/channel-socket: qio_channel_socket_flush(): improve msg validation
 * hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
 * target/arm: Fix A64 LDRA immediate decode

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# gpg: Signature made Mon 06 Nov 2023 23:31:33 HKT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20231106' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Fix A64 LDRA immediate decode
  hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
  io/channel-socket: qio_channel_socket_flush(): improve msg validation
  hw/core/loader: gunzip(): initialize z_stream
  block/nvme: nvme_process_completion() fix bound for cid
  mc146818rtc: rtc_set_time(): initialize tm to zeroes
  util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
  hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
  tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references
  hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables.
  tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2
  hw/arm/virt: fix PMU IRQ registration

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07 09:42:07 +08:00
Stefan Hajnoczi
bb59f3548f vfio queue:
* Support for non 64b IOVA space
 * Introduction of a PCIIOMMUOps callback structure to ease future
   extensions
 * Fix for a buffer overrun when writing the VF token
 * PPC cleanups preparing ground for IOMMUFD support
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Merge tag 'pull-vfio-20231106' of https://github.com/legoater/qemu into staging

vfio queue:

* Support for non 64b IOVA space
* Introduction of a PCIIOMMUOps callback structure to ease future
  extensions
* Fix for a buffer overrun when writing the VF token
* PPC cleanups preparing ground for IOMMUFD support

# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Mon 06 Nov 2023 22:35:30 HKT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [unknown]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-vfio-20231106' of https://github.com/legoater/qemu: (22 commits)
  vfio/common: Move vfio_host_win_add/del into spapr.c
  vfio/spapr: Make vfio_spapr_create/remove_window static
  vfio/container: Move spapr specific init/deinit into spapr.c
  vfio/container: Move vfio_container_add/del_section_window into spapr.c
  vfio/container: Move IBM EEH related functions into spapr_pci_vfio.c
  util/uuid: Define UUID_STR_LEN from UUID_NONE string
  util/uuid: Remove UUID_FMT_LEN
  vfio/pci: Fix buffer overrun when writing the VF token
  util/uuid: Add UUID_STR_LEN definition
  hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps
  test: Add some tests for range and resv-mem helpers
  virtio-iommu: Consolidate host reserved regions and property set ones
  virtio-iommu: Implement set_iova_ranges() callback
  virtio-iommu: Record whether a probe request has been issued
  range: Introduce range_inverse_array()
  virtio-iommu: Introduce per IOMMUDevice reserved regions
  util/reserved-region: Add new ReservedRegion helpers
  range: Make range_compare() public
  virtio-iommu: Rename reserved_regions into prop_resv_regions
  vfio: Collect container iova range info
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07 09:41:52 +08:00
Stefan Hajnoczi
17735e9371 Hyper-V Dynamic Memory protocol driver.
This driver is like virtio-balloon on steroids for Windows guests:
 it allows both changing the guest memory allocation via ballooning and
 inserting pieces of extra RAM into it on demand from a provided memory
 backend via Windows-native Hyper-V Dynamic Memory protocol.
 
 * Preparatory patches to support empty memory devices and ones with
 large alignment requirements.
 
 * Revert of recently added "hw/virtio/virtio-pmem: Replace impossible
 check by assertion" commit 5960f254db since this series makes this
 situation possible again.
 
 * Protocol definitions.
 
 * Hyper-V DM protocol driver (hv-balloon) base (ballooning only).
 
 * Hyper-V DM protocol driver (hv-balloon) hot-add support.
 
 * qapi query-memory-devices support for the driver.
 
 * qapi HV_BALLOON_STATUS_REPORT event.
 
 * The relevant PC machine plumbing.
 
 * New MAINTAINERS entry for the above.
 -----BEGIN PGP SIGNATURE-----
 
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 /YWWFWUD
 =RAb0
 -----END PGP SIGNATURE-----

Merge tag 'pull-hv-balloon-20231106' of https://github.com/maciejsszmigiero/qemu into staging

Hyper-V Dynamic Memory protocol driver.

This driver is like virtio-balloon on steroids for Windows guests:
it allows both changing the guest memory allocation via ballooning and
inserting pieces of extra RAM into it on demand from a provided memory
backend via Windows-native Hyper-V Dynamic Memory protocol.

* Preparatory patches to support empty memory devices and ones with
large alignment requirements.

* Revert of recently added "hw/virtio/virtio-pmem: Replace impossible
check by assertion" commit 5960f254db since this series makes this
situation possible again.

* Protocol definitions.

* Hyper-V DM protocol driver (hv-balloon) base (ballooning only).

* Hyper-V DM protocol driver (hv-balloon) hot-add support.

* qapi query-memory-devices support for the driver.

* qapi HV_BALLOON_STATUS_REPORT event.

* The relevant PC machine plumbing.

* New MAINTAINERS entry for the above.

# -----BEGIN PGP SIGNATURE-----
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# /YWWFWUD
# =RAb0
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Nov 2023 22:08:18 HKT
# gpg:                using RSA key E2776AABA08E26FF5A1B4A0952B1D6E951D0CE07
# gpg: Good signature from "Maciej S. Szmigiero <mail@maciej.szmigiero.name>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 727A 0D4D DB9E D9F6 039B  ECEF 847F 5E37 90CE 0977
#      Subkey fingerprint: E277 6AAB A08E 26FF 5A1B  4A09 52B1 D6E9 51D0 CE07

* tag 'pull-hv-balloon-20231106' of https://github.com/maciejsszmigiero/qemu:
  MAINTAINERS: Add an entry for Hyper-V Dynamic Memory Protocol
  hw/i386/pc: Support hv-balloon
  qapi: Add HV_BALLOON_STATUS_REPORT event and its QMP query command
  qapi: Add query-memory-devices support to hv-balloon
  Add Hyper-V Dynamic Memory Protocol driver (hv-balloon) hot-add support
  Add Hyper-V Dynamic Memory Protocol driver (hv-balloon) base
  Add Hyper-V Dynamic Memory Protocol definitions
  memory-device: Drop size alignment check
  Revert "hw/virtio/virtio-pmem: Replace impossible check by assertion"
  memory-device: Support empty memory devices

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07 09:41:42 +08:00
Stefan Hajnoczi
9f33cf2a89 GPU pull request
Includes:
 - [PATCH] virtio-gpu-rutabaga: Add empty interface to fix arm64 crash
 - [PATCH v2 0/4] Misc ati-vga patches
 - [PATCH v2 0/5] virtio-gpu: add blob migration support
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Merge tag 'gpu-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging

GPU pull request

Includes:
- [PATCH] virtio-gpu-rutabaga: Add empty interface to fix arm64 crash
- [PATCH v2 0/4] Misc ati-vga patches
- [PATCH v2 0/5] virtio-gpu: add blob migration support

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# TMXdPV7bepd49aaynpGFeADhfw==
# =k/gN
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Nov 2023 21:31:34 HKT
# gpg:                using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg:                issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg:                 aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276  F62D DAE8 E109 7596 9CE5

* tag 'gpu-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
  Revert "virtio-gpu: block migration of VMs with blob=true"
  virtio-gpu: add virtio-gpu/blob vmstate subsection
  virtio-gpu: move scanout restoration to post_load
  virtio-gpu: factor out restore mapping
  virtio-gpu: block migration of VMs with blob=true
  ati-vga: Implement fallback for pixman routines
  ati-vga: Add 30 bit palette access register
  ati-vga: Support unaligned access to GPIO DDC registers
  ati-vga: Fix aperture sizes
  virtio-gpu-rutabaga: Add empty interface to fix arm64 crash

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07 09:41:34 +08:00
Stefan Hajnoczi
54e97162db Bugfixes for emulated Xen support
Selected bugfixes for mainline and stable, especially to the per-vCPU
 local APIC vector delivery mode for event channel notifications, which
 was broken in a number of ways.
 
 The xen-block driver has been defaulting to the wrong protocol for x86
 guest, and this fixes that — which is technically an incompatible change
 but I'm fairly sure nobody relies on the broken behaviour (and in
 production I *have* seen guests which rely on the correct behaviour,
 which now matches the blkback driver in the Linux kernel).
 
 A handful of other simple fixes for issues which came to light as new
 features (qv) were being developed.
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 -----END PGP SIGNATURE-----

Merge tag 'pull-xenfv-stable-20231106' of git://git.infradead.org/users/dwmw2/qemu into staging

Bugfixes for emulated Xen support

Selected bugfixes for mainline and stable, especially to the per-vCPU
local APIC vector delivery mode for event channel notifications, which
was broken in a number of ways.

The xen-block driver has been defaulting to the wrong protocol for x86
guest, and this fixes that — which is technically an incompatible change
but I'm fairly sure nobody relies on the broken behaviour (and in
production I *have* seen guests which rely on the correct behaviour,
which now matches the blkback driver in the Linux kernel).

A handful of other simple fixes for issues which came to light as new
features (qv) were being developed.

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# 7uBKbVpdPKul0DY=
# =dQ7h
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Nov 2023 18:25:02 HKT
# gpg:                using RSA key BE07D9FD54809AB2C4B0FF5F63762CDA67E2F359
# gpg:                issuer "dwmw2@infradead.org"
# gpg: Good signature from "David Woodhouse <dwmw2@infradead.org>" [unknown]
# gpg:                 aka "David Woodhouse <dwmw2@exim.org>" [unknown]
# gpg:                 aka "David Woodhouse <david@woodhou.se>" [unknown]
# gpg:                 aka "David Woodhouse <dwmw2@kernel.org>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: BE07 D9FD 5480 9AB2 C4B0  FF5F 6376 2CDA 67E2 F359

* tag 'pull-xenfv-stable-20231106' of git://git.infradead.org/users/dwmw2/qemu:
  hw/xen: use correct default protocol for xen-block on x86
  hw/xen: take iothread mutex in xen_evtchn_reset_op()
  hw/xen: fix XenStore watch delivery to guest
  hw/xen: don't clear map_track[] in xen_gnttab_reset()
  hw/xen: select kernel mode for per-vCPU event channel upcall vector
  i386/xen: fix per-vCPU upcall vector for Xen emulation
  i386/xen: Don't advertise XENFEAT_supervisor_mode_kernel

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07 09:41:24 +08:00
Stefan Hajnoczi
b8cdbe0e4c Q800 pull request 20231106
macfb: A/UX fixes for colour LUT
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Merge tag 'q800-for-8.2-pull-request' of https://github.com/vivier/qemu-m68k into staging

Q800 pull request 20231106

macfb: A/UX fixes for colour LUT

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# gpg: Signature made Mon 06 Nov 2023 16:15:16 HKT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* tag 'q800-for-8.2-pull-request' of https://github.com/vivier/qemu-m68k:
  macfb: allow reads from the DAFB_LUT register
  macfb: allow larger write accesses to the DAFB_LUT register
  macfb: rename DAFB_RESET to DAFB_LUT_INDEX
  macfb: don't clear interrupts when writing to DAFB_RESET

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07 09:41:10 +08:00