Commit 36388314fe moved most of the
interrupt logic to cpu-exec.c. Remove the remaining useless code
and fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>
Tested-by: Edgar E. Iglesias <edgar@axis.com>
This patch adds support for loongson 2E & 2F instructions. They are the
same instructions, but differ by the opcode encoding.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add instruction decoding for the microMIPS ASE. All we do is decode and
then forward to the existing gen_* routines.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Change code handling mips16-specific branches to use ISA-neutral special
opcodes. Since there are several places where the delay slot
requirements for microMIPS branches differ from mips16 branches, using
opcodes is easier than checking hflags, then checking mips16
vs. microMIPS.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Move all knowledge about coprocessor-checking and register numbering
into the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add FMT_* constants for the floating-point format field in opcodes and
tweak a few places to use them. Add enums for various invocations of
FOP and tweak gen_farith and its lone caller accordingly.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In the previous patch which introduced fprintf_function to
allow parameter checking by gcc some compiler warnings
remained unfixed.
These warnings are fixed here.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
When we signal a CpU exception for coprocessor 0, we should indicate
that it's for coprocessor 0 instead of coprocessor 1.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Running programs with the MIPS user-mode emulator fails during dynamic
loading, as floating-point instructions are not enabled in in
env->hflags. Move the code for doing so from fpu_init to cpu_reset so
the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset
setting env->hflags to MIPS_HFLAG_UM.
The same end can be achieved by swapping the ordering of fpu_init and
cpu_reset in cpu_mips_init, but it seemed better to consolidate the
CONFIG_USER_ONLY code into a single location.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
There's no good way to add this incrementally, so we do it all at once.
The only changes to shared code are in handle_delay_slot. We need to
flip ISAMode when doing a jump-and-exchange. We also need to set
ISAMode the low bit of the target address for jump-to-register.
Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT,
make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want
basic information about a branch.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Move delay slot handling to common code whose invocation can be
controlled from gen_intermediate_code_internal.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This is a common pattern in existing code. We'll also use it to
implement the mips16 SAVE/RESTORE instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
It's easier to implement mips16 shift instructions if we're not
examining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRV
and do the special-case handling of SRL and SRLV inside decode_opc.
Likewise for their 64-bit counterparts.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Currently the ll/sc instructions use the virtual address in both
user and system mode. Use the physical address insteead in system
mode.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Remove cpu_mips_register()
- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()
- move the other parts in cpu_mips_init()
Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Now that MAX_OP_PER_INSTR has been increased to a safer value, removed
the target-mips specific workaround.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Single-stepping branches on MIPS didn't work right, because the
generation of EXCP_DEBUG happened after the generation of the code to
exit the current TB. That is, given the code:
bne v0,v1,target
nop
...
target:
addu v0,v0,v1
1:
when you single-stepped through the NOP, execution wouldn't actually
halt until you reached the label `1'.
This patch corrects that and also changes single-stepping so that a
branch and its delay slot are executed as one instruction for the
purposes of single-stepping. This behavior is comparable to what other
MIPS tools (e.g. MIPSsim with MDI) do. GDB avoids placing breakpoints
in branch delay slots, so this change doesn't break anything on the GDB
side.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.
Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Conditional moves off fp condition codes were using the result of
get_fp_bit to isolate and test the relevant condition code. However,
get_fp_bit returns the bit number of the condition code, not a
bitmask. (Compare the use of get_fp_bit in gen_compute_branch1, for
instance.)
Fixed by shifting a bitmask into place using the result of get_fp_bit in
the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}).
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix botched merge of op_ldst_sc calls to match actual implementation.
Thanks to Aurelien Jarno for diagnosing this.
Signed-off-by: Paul Brook <paul@codesourcery.com>
MADD was not correctly writing to HI.
MSUB/MSUBU are specified as `HI||LO - product', not `product - HI||LO'.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
