Commit Graph

429 Commits

Author SHA1 Message Date
Aurelien Jarno
2488b41bb2 tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
c8d80cef55 tcg/arm: replace integer values by registers enum
The TCG ARM backends uses integer values to refer to both immediate
values and register number. This makes the code difficult to read.

The patch below replaces all (if I haven't miss any ;-) integer values
representing register number by TCG_REG_* enum values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
f694a27ed7 tcg/arm: remove store signed functions
Store signed functions doesn't make sense, and are not used. Remove
them.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
e4a7d5e88c tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that are
clobbered or reserved one by one. This makes the code easier to read.

Also declare all the 16 registers to TCG, and mark pc as reserved.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
39221a82be tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to a
subroutine. According to the "Procedure Call Standard for the ARM
Architecture", it is the job of the callee to save this register.
Moreover, this register is already saved in the prologue/epilogue.

This patch removes the disabled SAVE_LR code, as there is no need to
reenable later.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
malc
606257c6f2 tcg/ppc: Remove redundant comparison from brcond2
Signed-off-by: malc <av1474@comtv.ru>
2010-04-18 08:46:29 +04:00
Richard Henderson
2d8ebcf94e Fix --enable-profiler compilation.
There's a header file inclusion ordering problem between cpu-all.h
and qemu-timer.h, such that cpu_get_real_ticks is not defined when
we attempt to use it in profile_getclock.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-17 16:25:10 +00:00
malc
655feed5d9 tcg: Add missing static qualifier
Build breaks otherwise when USE_LIVENESS_ANALYSIS is not defined.

Signed-off-by: malc <av1474@comtv.ru>
2010-04-17 08:00:41 +04:00
malc
efe72c8de7 tcg/ppc: Fix signed versions of brcond2
Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.

Signed-off-by: malc <av1474@comtv.ru>
2010-04-17 08:00:32 +04:00
Stefan Weil
60bf84cf4c tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilations
without optimisation, because the compiler makes heavy use
of this register (so the resulting code crashes).

Register s0 had been used for TCG_AREG1 in earlier releases,
but was no longer used and is now free for TCG_AREG0.

The resulting code works for compilations without
optimisation (tested with qemu mips in qemu mips
on x86 host).

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-14 00:59:42 +02:00
Aurelien Jarno
837d987bb9 tcg/README: improve description of bswap*
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-10 03:36:21 +02:00
Richard Henderson
3e1f46eaa4 tcg-hppa: Don't try to calls to non-constant addresses.
PA-RISC uses procedure descriptors.  We'd need to emit a call to
the millicode routine $$dyncall.  However, this situation doesn't
actually arise, since we always have the descriptor available at
TCG code generation time.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:57:16 +02:00
Richard Henderson
91493631fe tcg-hppa: Fix in/out register overlap in add2/sub2.
Handle the output log part overlapping the input high parts.
Also, improve sub2 to handle some constants the second input low part.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:57:14 +02:00
Richard Henderson
fd76e73a10 tcg-hppa: Finish the port.
Delete inline functions from tcg-target.h that don't need to be there,
move the others to tcg-target.c.  Add 'Z', 'I', 'J' constraints for
0, signed 11-bit, and signed 5-bit respectively.  Add GUEST_BASE support
similar to ppc64, with the value stored in a register.  Add missing
registers to reg_alloc_order.  Add support for 12-bit branch relocations.
Add functions for synthetic operations: addi, mtctl, dep, shd, vshd, ori,
andi, shifts, rotates, multiply, branches, setcond.  Split out TLB reads
from qemu_ld and qemu_st; fix argument loading for tlb external calls.
Generate the prologue.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
Aurelien Jarno
a175b996b2 tcg/ia64: fix tlb addend read
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
malc
98926b0a25 tcg/ppc64: Fix typo
Signed-off-by: malc <av1474@comtv.ru>
2010-04-07 02:26:22 +04:00
malc
f7e2aca834 tcg/ppc: Fix typo
Signed-off-by: malc <av1474@comtv.ru>
2010-04-06 03:10:03 +04:00
malc
a884dcb804 tcg/ppc: Implment bswap16/32
Signed-off-by: malc <av1474@comtv.ru>
2010-04-06 02:54:22 +04:00
Aurelien Jarno
116348def2 tcg/mips: use seb/seh instructions on MIPS32R2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05 15:16:44 +02:00
Aurelien Jarno
ba0d89bbeb tcg/mips: fix 64-bit linux-user on big endian MIPS
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05 15:16:44 +02:00
malc
aa77bebd98 tcg/ppc: Implement eqv, nand and nor
Signed-off-by: malc <av1474@comtv.ru>
2010-04-05 16:09:05 +04:00
Paul Brook
355b194369 Split TLB addend and target_phys_addr_t
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t).  However since the introduction of
the iotlb field it has only been used for RAM accesses.

This means we can change the type of addend to unsigned long, and remove
associated hacks in the big-endian TCG backends.

We can also remove the host dependence from target_phys_addr_t.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05 00:28:53 +01:00
malc
36368cf0d5 tcg/ppc: Fix not_i32
Thanks to Alexander Graf for bug report and a good reproducible test
case.

Signed-off-by: malc <av1474@comtv.ru>
2010-04-04 20:36:29 +04:00
Aurelien Jarno
a18f844fb5 tcg/TODO: remove setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-01 22:00:41 +02:00
Aurelien Jarno
477ba62001 tcg: initial ia64 support
A few words about design choices:
* On IA64, instructions should be grouped by bundle, and dependencies
  between instructions declared. A first version of this code tried to
  schedule instructions automatically, but was very complex and too
  invasive for the current common TCG code (ops not ending at
  instruction boundaries, code retranslation breaking already generated
  code, etc.)  It was also not very efficient, as dependencies between
  TCG ops is not available.
  Instead the option taken by the current implementation does not try
  to fill the bundle by scheduling instructions, but by providing ops
  not available as an ia64 instruction, and by offering 22-bit constant
  loading for most of the instructions. With both options the bundle are
  filled at approximately the same level.

* Up to 128 registers can be affected to a function on IA64, but TCG
  limits this number to 64, which is actually more than enough. The
  register affectation is the following:
  - r0: used to map a constant argument with value 0
  - r1: global pointer
  - r2, r3: internal use
  - r4 to r6: not used to avoid saving them
  - r7: env structure
  - r8 to r11: free for TCG (call clobbered)
  - r12: stack pointer
  - r13: thread pointer
  - r14 to r31: free for TCG (call clobbered)
  - r32: reserved (return address)
  - r33: reserved (PFS)
  - r33 to r63: free for TCG

* The IA64 architecture has only 64-bit registers and no 32-bit
  instructions (the only exception being cmp4). Therefore 64-bit
  registers and instructions are used for 32-bit ops. The adopted
  strategy is the same as the ABI, that is the higher 32 bits are
  undefined. Most ops (and, or, add, shl, etc.) can directly use
  the 64-bit registers, while some others have to sign-extend (sar,
  div, etc.) or zero-extend (shr, divu, etc.) the register first.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-01 21:51:59 +02:00
Aurelien Jarno
6d8ff4d85c tcg/mips: fix branch offset during retranslation
Branch offsets should only be overwritten during relocation, to support
partial retranslation.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-29 02:09:23 +02:00
Stefan Weil
1584c84574 tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860
did not change all occurrences of INDEX_op_qemu_ld32u
for tcg/arm.

Please note that I could not test this patch
(I have currently no arm system available).

Cc: Richard Henderson <rth@twiddle.net>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-28 16:39:52 +02:00
Aurelien Jarno
cc01cc8ea2 tcg-mips: add guest base support
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27 17:31:04 +01:00
Aurelien Jarno
489722cf3f tcg/mips: implement the not_i32 op the same way as gcc
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27 16:50:55 +01:00
Aurelien Jarno
2b79487a56 tcg-mips: implement nor
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27 16:32:55 +01:00
Richard Henderson
86feb1c860 tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand).  For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with
a given extension to a 64-bit result.  This distinction already
exists for the ld* loads, but not the qemu_ld* loads.

Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for
32-bit outputs.  Adjust all code generators to match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 23:01:03 +01:00
Richard Henderson
32d98fbd10 tcg: Allow target-specific implementation of NOR.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:52:44 +01:00
Richard Henderson
9940a96bc8 tcg: Allow target-specific implementation of NAND.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:44:40 +01:00
Richard Henderson
8d625cf1d1 tcg: Allow target-specific implementation of EQV.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:42:46 +01:00
Richard Henderson
a10f9f4f0c tcg: Use not_i32 to implement not_i64.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:29:12 +01:00
Richard Henderson
c02244a508 tcg: Change TCGType to an enumeration.
The TCGType name was already used consistently.  Changing it
to an enumeration instead of a set of defines aids debugging.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:29:10 +01:00
Richard Henderson
8a56e84091 tcg: Use TCGCond where appropriate.
Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:29:08 +01:00
Richard Henderson
a975160954 tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 21:28:24 +01:00
Paolo Bonzini
a63b5829af remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26 20:48:30 +01:00
Richard Henderson
3f90f252ec tcg-hppa: Fix 64-bit argument ordering
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23 22:00:47 +01:00
Aurelien Jarno
9e97d8e941 tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the address
of the env structure and is not modified by GCC.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20 12:27:42 +01:00
Aurelien Jarno
26c5d372e4 tcg/arm: fix load/store definitions for 32-bit targets
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20 12:10:20 +01:00
Aurelien Jarno
30138f2814 tcg: protect div2 in tcg/tcg-opc.h
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20 11:17:03 +01:00
Aurelien Jarno
dbfff4deb5 tcg: declare internal helpers as const and pure
TCG internal helpers only access to the values passed in arguments, and
do not modify the CPU internal state. Thus they can be declared as
const and pure.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14 23:01:01 +01:00
Aurelien Jarno
2b71cd72d3 tcg/arm: use helpers for divu/remu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14 22:04:54 +01:00
Aurelien Jarno
31d6655100 tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers for
div/rem/divu/remu.

Create a #define for div2 so that targets can select between
div, div2 and helper implementation. Use the helper version if none
of the #define are present.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14 22:04:50 +01:00
Blue Swirl
a6c6f76ceb Fix build with -DNDEBUG in CFLAGS
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13 14:18:50 +00:00
Aurelien Jarno
932234f64c tcg/arm: implement andc op
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:46:08 +01:00
Aurelien Jarno
a3f5054b1a tcg: update README with const and pure helpers
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:44:53 +01:00
Aurelien Jarno
4e17eae9f2 tcg/arm: correctly save/restore registers in prologue/epilogue
Since commit 6113d6d316 QEMU crashes
on ARM hosts. This is not a bug of this commit, but a latent bug
revealed by this commit.

The TCG code is called through a procedure call using the prologue
and epilogue code. This code does not save and restore enough registers.
The "Procedure Call Standard for the ARM Architecture" says:

  A subroutine must preserve the contents of the registers r4-r8, r10,
  r11 and SP (and r9 in PCS variants that designate r9 as v6).

The current code only saves and restores r9 to r11, and misses r4 to
r8. The patch fixes that by saving r4 to r12. Theoretically there is
no need to save and restore r12, but an even number of registers have
to be saved as per EABI.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:44:25 +01:00
Blue Swirl
65850a0254 Fix Sparc host build breakage
Fix error:
  CC    sparc-bsd-user/op_helper.o
In file included from /src/qemu/tcg/tcg.c:158:
/src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13 09:52:19 +00:00
malc
35f6b5997a tcg/ppc[64]: Only define addend load helpers in softmmu case
Signed-off-by: malc <av1474@comtv.ru>
2010-03-13 00:27:46 +03:00
Paul Brook
20cb400d41 Remove TLB from userspace
Remove TLB from userspace CPU structure.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:21 +00:00
Aurelien Jarno
d3f137e355 tcg/arm: merge the two sets of #define for optional ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02 23:12:42 +01:00
Aurelien Jarno
023e77f801 tcg/arm: accept immediate arguments for brcond/setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 22:31:57 +01:00
Andrzej Zaborowski
b525f0a94f Add a missing break 2010-03-02 22:26:04 +01:00
Aurelien Jarno
e0404769fa tcg/arm: implement setcond2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 22:19:26 +01:00
Aurelien Jarno
f72a6cd7c7 tcg/arm: implement setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 22:17:43 +01:00
Aurelien Jarno
6b6586131b tcg/arm: fix div2/divu2
When restoring register values, increase the stack register for skipped
values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02 20:19:18 +01:00
malc
d616cf1d15 tcg/ppc: Fix right rotation
Signed-off-by: malc <av1474@comtv.ru>
2010-02-27 02:00:00 +03:00
malc
98b8d951dc tcg/ppc: Fix typo
Signed-off-by: malc <av1474@comtv.ru>
2010-02-23 00:50:03 +03:00
malc
d34f4bafa6 tcg/ppc64: Use C90 style comments
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22 21:56:35 +03:00
malc
65fe043eb4 tcg/ppc: Implement some of the optional ops
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22 21:50:01 +03:00
Jay Foad
30c0c76ce0 tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <jay.foad@gmail.com>
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22 19:38:52 +03:00
Jay Foad
2c92d62ebb tcg: fix assertion with --enable-debug
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the
following assertion failure:

qemu-alpha: tcg/tcg.c:1055:
tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed.

Signed-off-by: Jay Foad <jay.foad@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 12:26:14 +02:00
Richard Henderson
3682825669 tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:35:12 +00:00
Richard Henderson
18c8f7a35d tcg-sparc: Implement ORC.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:34:42 +00:00
Richard Henderson
dc69960dd6 tcg-sparc: Implement ANDC.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:34:18 +00:00
Richard Henderson
791d1262e2 tcg: Optional target implementation of ORC.
Previously ORC was always implemented by tcg-op.h with
an explicit NOT opcode.  Allow a target implementation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:33:52 +00:00
Richard Henderson
241cbed4a9 tcg: Optional target implementation of ANDC.
Previously ANDC was always implemented by tcg-op.h with
an explicit NOT opcode.  Allow a target implementation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:33:31 +00:00
Richard Henderson
be6551b1e7 tcg-sparc: Implement not.
The fallback implementation of "ret = arg1 ^ -1" isn't ideal
because of the extra tcg op to load the minus one.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:32:35 +00:00
Richard Henderson
4b5a85c175 tcg-sparc: Implement neg.
The fallback implementation of "ret = 0 - arg1" isn't ideal,
first because of the extra tcg op to load the zero, and second
because we fail to handle zero as %g0 for arg1 of the sub.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20 08:31:50 +00:00
malc
6ec8523603 tcg/ppc: Consistently use calling convention selection macros
Signed-off-by: malc <av1474@comtv.ru>
2010-02-20 01:47:35 +03:00
Juergen Lock
5da79c86a3 Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}.
New version after malc's comments.  (This avoids having to do
  #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__
for the third case.)

Submitted by: Andreas Tobler <andreast@fgznet.ch>  (original version)

Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de>
Signed-off-by: malc <av1474@comtv.ru>
2010-02-20 01:37:33 +03:00
Stefan Weil
c68aaa1892 tcg: Add consistency checks for op definitions
When compiled with CONFIG_DEBUG_TCG, this code looks
for missing, duplicate and wrong entries in the
op definitions.

Errors will raise an assertion at program start
(all checks are done in the initial phase).

The current code contains such errors, at least for
i386 guest on i386 host.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-18 19:08:14 +00:00
Richard Henderson
dbfe80e1ea tcg-sparc: Implement setcond, setcond2.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16 17:53:34 +00:00
Richard Henderson
1c086220a6 tcg: Add tcg_swap_cond.
Returns the condition as if with swapped comparison operands.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16 17:52:12 +00:00
Aurelien Jarno
cca1af8c4d tcg/mips: fix crash in tcg_out_qemu_ld()
The address register is overriden when it corresponds to v0 and the fast
path is taken, which leads to a crash. Fix that by using the a0 register
instead.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 22:54:22 +01:00
Aurelien Jarno
434254aa5f tcg/mips: implement setcond2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09 01:01:35 +01:00
Aurelien Jarno
4cb2638218 tcg/mips: implement setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08 16:37:37 +01:00
Aurelien Jarno
5105c5564c tcg: move setcond* ops to non-optional section
setcond is not an optional op, move it to the non-optional section.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08 12:10:15 +01:00
Aurelien Jarno
add1e7ea61 tcg: add setcondi pseudo-op
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08 12:06:05 +01:00
malc
1cd62ae9f8 tcg/ppc64: implement setcond
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07 02:48:53 +03:00
malc
27a7797b09 tcg/ppc32: proper setcond implementation
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07 02:48:48 +03:00
malc
b0809bf7ca tcg/ppc32: implement setcond[2]
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07 02:18:06 +03:00
Richard Henderson
1d2699ae5a tcg-i386: Implement setcond.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 22:23:40 +01:00
Richard Henderson
f75b56c1ec tcg-i386: Implement small forward branches.
There are places, like brcond2, where we know that the destination
of a forward branch will be within 127 bytes.

Add the R_386_PC8 relocation type to support this.  Add a flag to
tcg_out_jxx and tcg_out_brcond* to enable it.  Set the flag in the
brcond2 label_next branches; pass along the input flag otherwise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 22:23:39 +01:00
Richard Henderson
8f9db67c84 tcg-x86_64: implement setcond
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:14:24 +01:00
Richard Henderson
401d466da9 tcg: add tcg_invert_cond
It is very handy to have a reliable mapping of a condition to its inverse.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:14:24 +01:00
Richard Henderson
be210acb41 tcg: generic support for conditional set
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:14:24 +01:00
Richard Henderson
a38e609c46 tcg: document double-word support opcodes.
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.
Place these in a new section that clearly indicates that they are
not to be emitted by translators.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:14:24 +01:00
Richard Henderson
09aac1266e tcg/x86_64: Avoid unnecessary REX.B prefixes.
The existing P_REXB internal opcode flag unconditionally emits
the REX prefix.  Technically it's not needed if the register in
question is %al, %bl, %cl, %dl.

Eliding the prefix requires splitting the P_REXB flag into two,
in order to indicate whether the byte register in question is
in the REG or the R/M field.  Within TCG, the byte register is
in the REG field only for stores.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-15 07:32:56 +01:00
Richard Henderson
5716990376 tcg/x86_64: Special-case all 32-bit AND operands.
This avoids an unnecessary REX.W prefix when dealing with AND
operands that fit into a 32-bit quantity.  The most common change
actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-14 18:16:40 +01:00
Richard Henderson
cc6dfecf02 tcg-sparc: Implement ext32[su]_i64
The 32-bit right-shift instructions is defined to extend the shifted
output to 64-bits.  A shift count of zero therefore is a simple
extension without actually shifting.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:34 +00:00
Richard Henderson
583d121520 tcg-sparc: Implement division properly.
The {div,divu}2 opcodes are intended for systems for which the
division instruction produces both quotient and remainder.  Sparc
is not such a system.  Indeed, the remainder must be computed as

  quot = a / b
  rem = a - (quot * b)

Split out a tcg_out_div32 function that properly initializes Y
with the extension of the input to 64-bits.  Discard the code
that used the 64-bit DIVX on sparc9/sparcv8plus without extending
the inputs to 64-bits.  Implement remainders in terms of division
followed by multiplication.

Signed-off-by: Richard Henderson <rth@twiddle.net>
[blauwirbel@gmail.com: applied rth's typo fix in tcg_out_div32]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:33 +00:00
Richard Henderson
5e143c43a6 tcg-sparc: Do not remove %o[012] from 'r' constraint.
Only 'L' constraint needs that.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:32 +00:00
Richard Henderson
7a3766f390 tcg-sparc: Implement add2, sub2, mulu2.
Add missing 32-bit double-word support opcodes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:31 +00:00
Richard Henderson
ba225198d0 tcg-sparc: Add tcg_out_arithc.
Add a function to handle the register-vs-immediate test for arithmetic.

Also, adjust the OP_32_64 macro so that it auto-indents properly.
Rename the gen_arith32 label to gen_arith, since it handles 64-bit
arithmetic as well.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:29 +00:00
Richard Henderson
ff44c2f3c8 tcg: Add tcg_unsigned_cond.
Returns an unsigned version of a signed condition;
returns the original condition otherwise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-27 09:09:41 +00:00
Richard Henderson
56f4927e34 tcg-sparc: Implement brcond2.
Split out tcg_out_cmp and properly handle immediate arguments.
Fix constraints on brcond to match what SUBCC accepts.
Add tcg_out_brcond2_i32 for 32-bit host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21 20:52:36 +00:00