tcg-sparc: Implement division properly.
The {div,divu}2 opcodes are intended for systems for which the
division instruction produces both quotient and remainder. Sparc
is not such a system. Indeed, the remainder must be computed as
quot = a / b
rem = a - (quot * b)
Split out a tcg_out_div32 function that properly initializes Y
with the extension of the input to 64-bits. Discard the code
that used the 64-bit DIVX on sparc9/sparcv8plus without extending
the inputs to 64-bits. Implement remainders in terms of division
followed by multiplication.
Signed-off-by: Richard Henderson <rth@twiddle.net>
[blauwirbel@gmail.com: applied rth's typo fix in tcg_out_div32]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson
Blue Swirl
parent
5e143c43a6
commit
583d121520
@ -243,7 +243,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
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#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
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#define WRY (INSN_OP(2) | INSN_OP3(0x30))
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#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
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#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
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#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
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#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
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@ -407,12 +407,9 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
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tcg_out_ldst(s, arg, arg1, arg2, STX);
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}
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static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
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static inline void tcg_out_sety(TCGContext *s, int rs)
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{
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if (val == 0 || val == -1)
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tcg_out32(s, WRY | INSN_IMM13(val));
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else
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fprintf(stderr, "unimplemented sety %ld\n", (long)val);
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tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
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}
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static inline void tcg_out_rdy(TCGContext *s, int rd)
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@ -444,6 +441,21 @@ static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
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}
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}
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static void tcg_out_div32(TCGContext *s, int rd, int rs1,
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int val2, int val2const, int uns)
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{
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/* Load Y with the sign/zero extension of RS1 to 64-bits. */
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if (uns) {
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tcg_out_sety(s, TCG_REG_G0);
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} else {
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tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
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tcg_out_sety(s, TCG_REG_I5);
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}
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tcg_out_arithc(s, rd, rs1, val2, val2const,
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uns ? ARITH_UDIV : ARITH_SDIV);
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}
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static inline void tcg_out_nop(TCGContext *s)
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{
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tcg_out_sethi(s, TCG_REG_G0, 0);
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@ -1113,24 +1125,22 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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case INDEX_op_mul_i32:
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c = ARITH_UMUL;
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goto gen_arith;
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case INDEX_op_div2_i32:
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#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
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c = ARITH_SDIVX;
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goto gen_arith;
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#else
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tcg_out_sety(s, 0);
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c = ARITH_SDIV;
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goto gen_arith;
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#endif
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case INDEX_op_divu2_i32:
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#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
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c = ARITH_UDIVX;
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goto gen_arith;
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#else
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tcg_out_sety(s, 0);
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c = ARITH_UDIV;
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goto gen_arith;
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#endif
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case INDEX_op_div_i32:
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tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
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break;
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case INDEX_op_divu_i32:
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tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
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break;
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case INDEX_op_rem_i32:
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case INDEX_op_remu_i32:
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tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
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opc == INDEX_op_remu_i32);
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tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
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ARITH_UMUL);
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tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
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break;
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case INDEX_op_brcond_i32:
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tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
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@ -1214,12 +1224,20 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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case INDEX_op_mul_i64:
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c = ARITH_MULX;
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goto gen_arith;
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case INDEX_op_div2_i64:
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case INDEX_op_div_i64:
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c = ARITH_SDIVX;
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goto gen_arith;
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case INDEX_op_divu2_i64:
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case INDEX_op_divu_i64:
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c = ARITH_UDIVX;
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goto gen_arith;
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case INDEX_op_rem_i64:
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case INDEX_op_remu_i64:
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tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
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opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
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tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
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ARITH_MULX);
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tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
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break;
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case INDEX_op_brcond_i64:
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tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
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@ -1263,8 +1281,10 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_add_i32, { "r", "r", "rJ" } },
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{ INDEX_op_mul_i32, { "r", "r", "rJ" } },
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{ INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
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{ INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
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{ INDEX_op_div_i32, { "r", "r", "rJ" } },
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{ INDEX_op_divu_i32, { "r", "r", "rJ" } },
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{ INDEX_op_rem_i32, { "r", "r", "rJ" } },
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{ INDEX_op_remu_i32, { "r", "r", "rJ" } },
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{ INDEX_op_sub_i32, { "r", "r", "rJ" } },
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{ INDEX_op_and_i32, { "r", "r", "rJ" } },
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{ INDEX_op_or_i32, { "r", "r", "rJ" } },
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@ -1312,8 +1332,10 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_add_i64, { "r", "r", "rJ" } },
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{ INDEX_op_mul_i64, { "r", "r", "rJ" } },
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{ INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
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{ INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
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{ INDEX_op_div_i64, { "r", "r", "rJ" } },
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{ INDEX_op_divu_i64, { "r", "r", "rJ" } },
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{ INDEX_op_rem_i64, { "r", "r", "rJ" } },
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{ INDEX_op_remu_i64, { "r", "r", "rJ" } },
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{ INDEX_op_sub_i64, { "r", "r", "rJ" } },
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{ INDEX_op_and_i64, { "r", "r", "rJ" } },
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{ INDEX_op_or_i64, { "r", "r", "rJ" } },
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@ -88,6 +88,9 @@ enum {
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#endif
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32
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#define TCG_TARGET_HAS_div_i64
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//#define TCG_TARGET_HAS_bswap32_i32
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//#define TCG_TARGET_HAS_bswap64_i64
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//#define TCG_TARGET_HAS_neg_i32
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