tcg/x86_64: Avoid unnecessary REX.B prefixes.
The existing P_REXB internal opcode flag unconditionally emits the REX prefix. Technically it's not needed if the register in question is %al, %bl, %cl, %dl. Eliding the prefix requires splitting the P_REXB flag into two, in order to indicate whether the byte register in question is in the REG or the R/M field. Within TCG, the byte register is in the REG field only for stores. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -217,9 +217,10 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define JCC_JLE 0xe
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#define JCC_JG 0xf
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#define P_EXT 0x100 /* 0x0f opcode prefix */
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#define P_REXW 0x200 /* set rex.w = 1 */
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#define P_REXB 0x400 /* force rex use for byte registers */
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#define P_EXT 0x100 /* 0x0f opcode prefix */
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#define P_REXW 0x200 /* set rex.w = 1 */
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#define P_REXB_R 0x400 /* REG field as byte register */
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#define P_REXB_RM 0x800 /* R/M field as byte register */
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static const uint8_t tcg_cond_to_jcc[10] = {
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[TCG_COND_EQ] = JCC_JE,
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@ -234,16 +235,29 @@ static const uint8_t tcg_cond_to_jcc[10] = {
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[TCG_COND_GTU] = JCC_JA,
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};
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static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
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static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
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{
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int rex;
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rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) |
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((x >> 2) & 2) | ((rm >> 3) & 1);
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if (rex || (opc & P_REXB)) {
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tcg_out8(s, rex | 0x40);
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int rex = 0;
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rex |= (opc & P_REXW) >> 6; /* REX.W */
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rex |= (r & 8) >> 1; /* REX.R */
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rex |= (x & 8) >> 2; /* REX.X */
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rex |= (rm & 8) >> 3; /* REX.B */
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/* P_REXB_{R,RM} indicates that the given register is the low byte.
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For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
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as otherwise the encoding indicates %[abcd]h. Note that the values
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that are ORed in merely indicate that the REX byte must be present;
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those bits get discarded in output. */
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rex |= opc & (r >= 4 ? P_REXB_R : 0);
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rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
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if (rex) {
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tcg_out8(s, (uint8_t)(rex | 0x40));
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}
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if (opc & P_EXT)
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if (opc & P_EXT) {
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tcg_out8(s, 0x0f);
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}
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tcg_out8(s, opc & 0xff);
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}
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@ -408,7 +422,7 @@ static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
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tcg_out8(s, val);
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} else if (c == ARITH_AND && val == 0xffu) {
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/* movzbl */
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tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
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tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, r0, r0);
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} else if (c == ARITH_AND && val == 0xffffu) {
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/* movzwl */
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tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
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@ -776,7 +790,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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switch(opc) {
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case 0:
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/* movzbl */
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tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
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tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, TCG_REG_RSI, data_reg);
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break;
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case 1:
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/* movzwl */
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@ -829,7 +843,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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switch(opc) {
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case 0:
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/* movb */
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tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, offset);
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tcg_out_modrm_offset(s, 0x88 | P_REXB_R, data_reg, r0, offset);
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break;
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case 1:
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if (bswap) {
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@ -964,7 +978,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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case INDEX_op_st8_i32:
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case INDEX_op_st8_i64:
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/* movb */
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tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]);
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tcg_out_modrm_offset(s, 0x88 | P_REXB_R, args[0], args[1], args[2]);
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break;
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case INDEX_op_st16_i32:
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case INDEX_op_st16_i64:
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@ -1161,7 +1175,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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break;
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case INDEX_op_ext8s_i32:
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tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]);
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tcg_out_modrm(s, 0xbe | P_EXT | P_REXB_RM, args[0], args[1]);
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break;
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case INDEX_op_ext16s_i32:
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tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
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@ -1177,7 +1191,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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break;
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case INDEX_op_ext8u_i32:
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case INDEX_op_ext8u_i64:
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tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, args[0], args[1]);
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tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, args[0], args[1]);
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break;
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case INDEX_op_ext16u_i32:
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case INDEX_op_ext16u_i64:
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