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159 Commits

Author SHA1 Message Date
Richard Henderson
27721dbb7a target/arm: Implement SVE bitwise shift by vector (predicated) 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
ccd841c3d7 target/arm: Implement SVE bitwise shift by immediate (predicated) 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
047cec971d target/arm: Implement SVE Integer Reduction Group 
Excepting MOVPRFX, which isn't a reduction.  Presumably it is
placed within the group because of its encoding.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
f97cfd596e target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
028e2a7b87 target/arm: Implement SVE Predicate Misc Group 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
516e246a1a target/arm: Implement SVE Predicate Logical Operations Group 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
9e18d7a67f target/arm: Implement SVE predicate test 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
d1822297f6 target/arm: Implement SVE load vector/predicate 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00
Richard Henderson
38388f7ee3 target/arm: Add SVE decode skeleton 
Including only 4, as-yet unimplemented, instruction patterns
so that the whole thing compiles.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2018-05-18 17:48:08 +01:00