38388f7ee3
Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
46 lines
1.9 KiB
Plaintext
46 lines
1.9 KiB
Plaintext
# AArch64 SVE instruction descriptions
|
|
#
|
|
# Copyright (c) 2017 Linaro, Ltd
|
|
#
|
|
# This library is free software; you can redistribute it and/or
|
|
# modify it under the terms of the GNU Lesser General Public
|
|
# License as published by the Free Software Foundation; either
|
|
# version 2 of the License, or (at your option) any later version.
|
|
#
|
|
# This library is distributed in the hope that it will be useful,
|
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
# Lesser General Public License for more details.
|
|
#
|
|
# You should have received a copy of the GNU Lesser General Public
|
|
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
#
|
|
# This file is processed by scripts/decodetree.py
|
|
#
|
|
|
|
###########################################################################
|
|
# Named attribute sets. These are used to make nice(er) names
|
|
# when creating helpers common to those for the individual
|
|
# instruction patterns.
|
|
|
|
&rrr_esz rd rn rm esz
|
|
|
|
###########################################################################
|
|
# Named instruction formats. These are generally used to
|
|
# reduce the amount of duplication between instruction patterns.
|
|
|
|
# Three operand with unused vector element size
|
|
@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
|
|
|
|
###########################################################################
|
|
# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
|
|
|
|
### SVE Logical - Unpredicated Group
|
|
|
|
# SVE bitwise logical operations (unpredicated)
|
|
AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
|
|
ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
|
|
EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
|
|
BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
|