d1822297f6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
66 lines
2.5 KiB
Plaintext
66 lines
2.5 KiB
Plaintext
# AArch64 SVE instruction descriptions
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#
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# Copyright (c) 2017 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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###########################################################################
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# Named fields. These are primarily for disjoint fields.
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%imm9_16_10 16:s6 10:3
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###########################################################################
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# Named attribute sets. These are used to make nice(er) names
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# when creating helpers common to those for the individual
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# instruction patterns.
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&rri rd rn imm
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&rrr_esz rd rn rm esz
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###########################################################################
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# Named instruction formats. These are generally used to
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# reduce the amount of duplication between instruction patterns.
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# Three operand with unused vector element size
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@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
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# Basic Load/Store with 9-bit immediate offset
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@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
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&rri imm=%imm9_16_10
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@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
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&rri imm=%imm9_16_10
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###########################################################################
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# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
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### SVE Logical - Unpredicated Group
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# SVE bitwise logical operations (unpredicated)
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AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
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### SVE Memory - 32-bit Gather and Unsized Contiguous Group
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# SVE load predicate register
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LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
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# SVE load vector register
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LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
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