Commit Graph

805 Commits

Author SHA1 Message Date
Richard Henderson
fe7e1d3ec4 tcg: Fix !USE_DIRECT_JUMP
Commit 6375e09e changed the type of TranslationBlock.tb_next,
but failed to change the type of TCGContext.tb_next.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21 19:53:17 +02:00
Richard Henderson
5d8f536300 tcg: Optimize two-address commutative operations
While swapping constants to the second operand, swap
sources matching destinations to the first operand.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21 19:53:17 +02:00
Richard Henderson
fa01a2084e tcg: Optimize movcond for constant comparisons
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21 19:53:17 +02:00
Richard Henderson
d0a16297c9 tcg-i386: Implement movcond
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21 19:53:17 +02:00
Richard Henderson
ffc5ea09af tcg: Introduce movcond
Implemented with setcond if the target does not provide
the optional opcode.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21 19:53:16 +02:00
Aurelien Jarno
a255066039 tcg/optimize: fix end of basic block detection
Commit e31b0a7c05 fixed copy propagation on
32-bit host by restricting the copy between different types. This was the
wrong fix.

The real problem is that the all temps states should be reset at the end
of a basic block. This was done by adding such operations in the switch,
but brcond2 was forgotten (that's why the crash was only observed on 32-bit
hosts).

Fix that by looking at the TCG_OPF_BB_END instead. We need to keep the case
for op_set_label as temps might be modified through another path.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:53:46 +02:00
Aurelien Jarno
d104bebd07 revert "TCG: fix copy propagation"
Given the copy propagation breakage on 32-bit hosts has been fixed
commit e31b0a7c05 can be reverted.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:47 +02:00
Aurelien Jarno
332864bd95 tcg: mark set_label with TCG_OPF_BB_END flag
set_label is effectively the end of a basic block, as no optimization
can be made accross it. It was treated as such in the liveness analysis
code, but as a special case.

Mark it with TCG_OPF_BB_END flag so that this information can be used
by other parts of the TCG code, and remove the special case in the liveness
analysis code.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:46 +02:00
Aurelien Jarno
5c2d2a9ee5 tcg/i386: allow constants in load/store ops
On x86, it is possible to move a constant value to memory. Add code to
handle a constant argument to load/store ops.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-19 21:40:46 +02:00
Blue Swirl
89c33337fd Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.

Remove dyngen-exec.h and all references to it. Although included by
hw/spapr_hcall.c, it does not seem to use it.

Remove unused HELPER_CFLAGS.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-09-15 17:51:14 +00:00
Aurelien Jarno
fedc0da251 tcg/optimize: fix if/else/break coding style
optimizer.c contains some cases were the break is appearing in both the
if and the else parts. Fix that by moving it to the outer part. Also
move some common code there.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:06:04 +02:00
Aurelien Jarno
fbeaa26c4c tcg/optimize: add constant folding for brcond
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:06:03 +02:00
Aurelien Jarno
f8dd19e5c7 tcg/optimize: add constant folding for setcond
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:06:01 +02:00
Aurelien Jarno
65a7cce17d tcg/optimize: swap brcond/setcond arguments when possible
brcond and setcond ops are not commutative, but it's easy to compute the
new condition after swapping the arguments. Try to always put the constant
argument in second position like for commutative ops, to help backends to
generate better code.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:05:59 +02:00
Aurelien Jarno
01ee5282ea tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
shift/rot r, 0, a is equivalent to movi r, 0.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:05:58 +02:00
Aurelien Jarno
61251c0c79 tcg/optimize: simplify and r, a, 0 cases
and r, a, 0 is equivalent to a movi r, 0.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:05:57 +02:00
Aurelien Jarno
38ee188b1b tcg/optimize: simplify or/xor r, a, 0 cases
or/xor r, a, 0 is equivalent to a mov r, a.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:05:56 +02:00
Aurelien Jarno
56e4943825 tcg/optimize: split expression simplification
Split expression simplification in multiple parts so that a given op
can appear multiple times. This patch should not change anything.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:05:55 +02:00
Aurelien Jarno
c5cc28ff8f tcg: improve profiler
Now that there are two passes of optimization (optimize.c, liveness)
there is no point of outputing the statistics of the liveness part
only. Update the code to take into account both optimizations.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-11 18:05:52 +02:00
Aurelien Jarno
6845df48ce tcg/s390: fix ld/st with CONFIG_TCG_PASS_AREG0
The load/store slow path has been broken in e141ab52d:
- We need to move 4 registers for store functions and 3 registers for
  load functions and not the reverse.
- According to the s390x calling convention the arguments of a function
  should be zero extended. This means that the register shift should be
  done with TCG_TYPE_I64 to ensure the higher word is correctly zero
  extended when needed.

I am aware that CONFIG_TCG_PASS_AREG0 is being removed and thus that
this patch can be improved, but doing so means it can also be applied to
the 1.1 and 1.2 stable branches.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-09-10 13:38:33 +02:00
Aurelien Jarno
18fec301cd tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 code
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers was
broken in that it did not respect the ABI requirement that 64
bit values were passed in even-odd register pairs. The simplest
way to fix this is to implement some new utility functions
for marshalling function arguments into the correct registers
and stack, so that the code which sets up the address and
data arguments does not need to care whether there has been
a preceding env argument.

Based on commit 9716ef3b for ARM by Peter Maydell.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-08-28 20:38:39 +02:00
Aurelien Jarno
d03c98d80f tcg/ia64: fix and optimize ld/st slow path
Store slow path has been broken in e141ab52d:
- the arguments are shifted before the last one (mem_index) is written.
- the shift is done for both slow and fast paths.

Fix that. Also optimize a bit by bundling the move together. This still
can be optimized, but it's better to wait for a decision to be taken on
the arguments order.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-26 21:10:37 +02:00
Aurelien Jarno
18d445b443 tcg/ia64: fix prologue/epilogue
Prologue and epilogue code has been broken in cea5f9a28.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-08-26 21:10:28 +02:00
Peter Maydell
9716ef3b1b tcg/arm: Fix broken CONFIG_TCG_PASS_AREG0 code
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers was
broken in that it did not respect the ABI requirement that 64
bit values were passed in even-odd register pairs. The simplest
way to fix this is to implement some new utility functions
for marshalling function arguments into the correct registers
and stack, so that the code which sets up the address and
data arguments does not need to care whether there has been
a preceding env argument.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-08-26 18:14:46 +00:00
Scott Wood
3c01ae0ea2 tci: don't write zero for reloc in tci_out_label
If tci_out_label is called in the context of tcg_gen_code_search_pc, we
could be overwriting an already patched relocation with zero -- and not
repatch it because the set_label is past search_pc, causing a QEMU crash
when it tries to branch to a zero label.

Not writing anything to the relocation area seems to be in line with what
other backends do from the couple I looked at (x86, ppc).

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-24 12:19:24 +00:00
Alexander Graf
affe518990 TCG: Fix compile breakage in tcg_dump_ops
Commit eeacee4d86 changed the syntax of tcg_dump_ops, but didn't convert
all users (notably missing the ppc ones) to it. Fix them to the new syntax.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: malc <av1474@comtv.ru>
2012-06-24 02:54:33 +04:00
Blue Swirl
eeacee4d86 qemu-log: cleanup
Don't use global variables directly but via accessor functions. Rename globals.

Convert macros to functions, add GCC format attributes.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-21 18:45:18 +00:00
Andreas Färber
24f50d7ea5 tcg/ppc: Handle _CALL_DARWIN being undefined on Darwin
powerpc-apple-darwin9-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5577)
does not define _CALL_DARWIN, leading to unexpected behavior w.r.t.
register clobbering and stack frame layout.

Since _CALL_DARWIN is a reserved identifier, define a custom
TCG_TARGET_CALL_DARWIN based on either _CALL_DARWIN or __APPLE__.

Signed-off-by: Andreas F?rber <andreas.faerber@web.de>
Signed-off-by: malc <av1474@comtv.ru>
2012-05-27 21:52:56 +04:00
Andreas Färber
f4f7d01a3a tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0
In qemu_ld/st load the registers for the helper calls directly rather
than rotating them around afterwards for AREG0.

Also clobber the additional register.

Signed-off-by: Andreas F?rber <afaerber@suse.de>
Signed-off-by: malc <av1474@comtv.ru>
2012-05-15 00:53:31 +04:00
Andreas Färber
c82e5848e2 tcg/ppc64: Don't hardcode register numbers for qemu_ld/st
Facilitates using r3 for prepended AREG0.

Signed-off-by: Andreas F?rber <afaerber@suse.de>
Signed-off-by: malc <av1474@comtv.ru>
2012-05-15 00:53:31 +04:00
Andreas Färber
1b3e76ebd1 tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode
Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
based on patches by malc.

Also adjust the registers clobbered, based on patch by Alex.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Alexander Graf <agraf@suse.de>
[AF: Do not hardcode r3 for AREG0, requested by Alex]
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-05-09 13:59:19 -05:00
Andreas Färber
a082615b07 tcg/ppc: Clobber r5 for 64-bit qemu_ld
This accounts for the additional addr_reg2 register.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-05-09 13:59:19 -05:00
Andreas Färber
d831fdb051 tcg/ppc: Don't hardcode register numbers
Also assure i64 alignment where necessary.

Alignment code optimization suggested by malc.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-05-09 13:59:19 -05:00
Andreas Färber
c1696d94c1 tcg/ppc: Do not overwrite lower address word on Darwin and AIX
For targets where TARGET_LONG_BITS != 32, i.e. 64-bit guests,
addr_reg is moved to r4. For hosts without TCG_TARGET_CALL_ALIGN_ARGS
either data_reg2 or data_reg or a masked version thereof would overwrite
r4. Place it in r5 instead, matching TCG_TARGET_CALL_ALIGN_ARGS hosts.

This fixes immediate crashes of 64-bit guests observed on Darwin/ppc but
not on Darwin/ppc64.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Acked-by: malc <av1474@comtv.ru>
Acked-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-05-09 13:59:18 -05:00
malc
f05ae5379e Bail out if CONFIG_TCG_PASS_AREG0 is defined
Signed-off-by: malc <av1474@comtv.ru>
2012-05-03 15:48:49 +04:00
malc
f6af014e71 Restore consistent formatting
Signed-off-by: malc <av1474@comtv.ru>
2012-05-03 15:47:39 +04:00
Stefan Weil
8d918718ed tcg/i386: Add support for w64 ABI
w64 uses the registers rcx, rdx, r8 and r9 for function arguments,
so it needs a different declaration of tcg_target_call_iarg_regs.

rax, rcx, rdx, r8, r9, r10 and r11 may be changed by function calls.

rbx, rbp, rdi, rsi, r12, r13, r14 and r15 remain unchanged by function calls.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-04-15 21:25:15 +02:00
Stefan Weil
c170cb6649 tcg/i386: Use GDB JIT debugging interface only for hosts with ELF
Not all i386 / x86_64 hosts use ELF.
Ask the compiler whether ELF is used.

On w64, gdb crashes when ELF_HOST_MACHINE is defined.

Cc: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-04-15 21:25:15 +02:00
Li Zhang
f638f0d3ae qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs
There two entries of INDEX_op_ld_i64 in the ppc_op_defs.  That causes an
assertion failure in tcg_add_target_add_op_defs() when --enable-debug is
used on a ppc64 backend (that's ppc64 host, not target).

Signed-off-by: Li Zhang <zhlcindy@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: malc <av1474@comtv.ru>
2012-03-29 11:10:08 +04:00
Richard Henderson
cb1977d308 tcg-sparc: Add debug_frame support.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24 19:57:58 +00:00
Richard Henderson
e7bd630064 tcg-hppa: Add debug_frame support.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24 19:57:46 +00:00
Richard Henderson
abbb3eae10 tcg: Allow ELF_HOST_FLAGS and ELF_OSABI overrides in gdb-jit.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24 19:57:32 +00:00
Richard Henderson
5872bbf24e tcg: Add debug_info to JIT ELF image.
This allows us to actually supply a function name in softmmu builds;
gdb doesn't pick up the minimal symbol table otherwise.  Also add a
bit of documentation and statically generate more of the ELF image.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24 19:57:12 +00:00
Richard Henderson
813da6277c tcg: Use the GDB JIT debugging interface.
This allows us to generate unwind info for the dynamicly generated
code in the code_gen_buffer.  Only i386 is converted at this point.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-24 13:07:48 +00:00
Blue Swirl
5bd33de663 tcg: fix sparc host for AREG0 free operation
e141ab52d2 didn't handle
the other memory access helper case, fix.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 19:15:32 +00:00
Blue Swirl
e141ab52d2 softmmu templates: optionally pass CPUState to memory access functions
Optionally, make memory access helpers take a parameter for CPUState
instead of relying on global env.

On most targets, perform simple moves to reorder registers. On i386,
switch from regparm(3) calling convention to standard stack-based
version.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:21:52 +00:00
Blue Swirl
6a18ae2d29 i386: Remove REGPARM
Use stack based calling convention (GCC default) for interfacing with
generated code instead of register based convention (regparm(3)).

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18 12:21:48 +00:00
Stefan Weil
69784eaec3 w64: Fix data type of next_tb and tcg_qemu_tb_exec
next_tb is the numeric value of a tcg target (= QEMU host) address.

Using tcg_target_ulong instead of unsigned long shows this and makes
the code portable for hosts with an unusual size of long (w64).

The type cast '(long)(next_tb & ~3)' was not needed (casting
unsigned long to long does not change the bits, and nor does
casting long to pointer for most (= all non w64) hosts.
It is removed here.

Macro or function tcg_qemu_tb_exec is used to set next_tb.
The function also returns next_tb. Therefore tcg_qemu_tb_exec
must return a tcg_target_ulong.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-17 13:02:03 +00:00
Kirill Batuzov
4055299ef0 Fix large memory chunks allocation with tcg_malloc.
An attempt to allocate a large memory chunk after a small one resulted in
circular links in list of pools.  It caused the same memory being
allocated twice for different arrays.

Now pools for large memory chunks are kept in separate list and are
freed during pool reset because current allocator can not reuse them.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-17 12:57:48 +00:00
Andreas Färber
9349b4f9fd Rename CPUState -> CPUArchState
Scripted conversion:
  for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
    sed -i "s/CPUState/CPUArchState/g" $file
  done

All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
once all targets are QOM'ified and common fields have been extracted.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:27 +01:00
Stefan Weil
9d6fca70c7 tcg: Improve tcg_out_label and fix its usage for w64
tcg_out_label is always called with a third argument of pointer type
which was casted to tcg_target_long.

These casts can be avoided by changing the prototype of tcg_out_label.

There was also a cast to long. For most hosts with
sizeof(long) == sizeof(tcg_target_long) == sizeof(void *) this did not
matter, but for w64 it was wrong. This is fixed now.

Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-11 11:28:39 +00:00
Stefan Weil
2aeabc0817 w64: fix type casts when calling flush_icache_range
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-03 18:10:23 +00:00
Stefan Weil
dba4f1bcc3 w64: Change data type of parameters for flush_icache_range
The TCG targets i386 and tci needed a change of the function
prototype for w64.

This change is currently not needed for the other TCG targets,
but it can be applied to avoid code differences.

Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-03 18:10:21 +00:00
Stefan Weil
f57a516039 w64: Fix data type of parameters for flush_icache_range
flush_icache_range takes two address parameters which must be large
enough to address any address of the host.

For hosts with sizeof(unsigned long) == sizeof(void *), this patch
changes nothing. All currently supported hosts fall into this category.

For w64 hosts, sizeof(unsigned long) is 4 while sizeof(void *) is 8,
so the use of tcg_target_ulong is needed for i386 and tci (the tcg
targets which work with w64).

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-03 18:10:19 +00:00
Stefan Weil
c38bb94a99 tcg: Rearrange definitions and include statements
This change makes tcg_target_ulong available in tcg-target.h.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-03 18:10:17 +00:00
Stefan Weil
a97e45c8b8 tcg: Remove unneeded include statements
The standard include files are already included in qemu-common.h.

malloc.h and alloca.h were needed for alloca() which was removed
from TCG code some years ago when switching from dyngen to TCG
(see commit 49516bc0d6).

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-02-23 08:59:51 +00:00
Aurelien Jarno
5c84bd904b tcg-arm: fix a typo in comments
ARM still doesn't support 16GB buffers in 32-bit modes, replace the
16GB by 16MB in the comment.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-01-13 10:36:59 +00:00
Peter Maydell
05b922dd0a tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointer
On ARM, in Thumb mode r7 is used for the framepointer; this meant
that we would fail to compile in debug mode because we were using r7
for TCG_AREG0. Shift to r6 instead to avoid this clash.
(Bug reported as LP:870990.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2012-01-10 17:52:49 +01:00
Dr. David Alan Gilbert
222f23f508 tcg/arm: remove fixed map code buffer restriction
On ARM, don't map the code buffer at a fixed location, and fix up the
call/goto tcg routines to let it do long jumps.

Mapping the code buffer at a fixed address could sometimes result in it being
mapped over the top of the heap with pretty random results.

Signed-off-by: Dr. David Alan Gilbert <david.gilbert@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-12-14 21:58:18 +01:00
Peter Maydell
73f5e3132a tcg: make tcg_const_ptr actually accept a pointer argument
Make tcg_const_ptr() include a cast so that you can pass it a
pointer. This allows us to drop the casts we had in all the places
that use this macro.

Acked-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-14 11:13:03 +00:00
Stefan Weil
46d5dee007 tcg: Remove redundant declarations of TCG_TARGET_REG_BITS
TCG_TARGET_REG_BITS is declared in tcg.h for all TCG targets.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-09 10:03:39 +00:00
Dong Xu Wang
9814dd2795 fix spelling in tcg sub directory
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-02 10:50:57 +00:00
Stefan Weil
51711aee8c tci: Make flush_icache_range() inline
This is standard for other tcg targets and improves tci, too.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-11-28 11:36:34 -06:00
Richard Henderson
b08d26b76d tcg-sparc: Fix set-but-not used warnings.
In both cases, val is computed, but then not used in the
subsequent line, which then re-computes the quantity in
a different type (int32_t vs unsigned long).

Keep the computation type that's been working so far.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-19 11:20:26 +00:00
Blue Swirl
25cc4a768d Merge branch 's390-1.0' of git://repo.or.cz/qemu/agraf
* 's390-1.0' of git://repo.or.cz/qemu/agraf:
  s390x: initialize virtio dev region
  tcg: Use TCGReg for standard tcg-target entry points.
  tcg: Standardize on TCGReg as the enum for hard registers
  s390x: Add shutdown for TCG s390-virtio machine
  s390: Fix cpu shutdown for KVM
  s390: fix short kernel command lines
  s390: fix reset hypercall to reset the status
  s390x: implement SIGP restart and shutdown
  s390x: implement rrbe instruction properly
  s390x: update R and C bits in storage key
  s390x: make ipte 31-bit aware
  s390x: add ldeb instruction
2011-11-19 11:17:58 +00:00
Richard Henderson
2a534aff30 tcg: Use TCGReg for standard tcg-target entry points.
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-14 17:47:27 +01:00
Richard Henderson
771142c2a7 tcg: Standardize on TCGReg as the enum for hard registers
Most targets did not name the enum; tci used TCGRegister.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-14 17:47:26 +01:00
David Gibson
9df3b45dd4 tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6
tcg/ppc64/tcg-target.c has a couple of places where variables are set
unconditionally, but otherwise used only for softmmu builds, not
userspace only builds.  This causes compiler warnings (which are fatal
by default) when compiling for a ppc64 host with gcc 4.6.  This patch
fixes the problem by moving the code which defines and sets the
variables into the CONFIG_SOFTMMU guarded regions.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-11 17:33:58 +01:00
Blue Swirl
c51d9cb5b6 Merge branch 'tci' of git://qemu.weilnetz.de/qemu
* 'tci' of git://qemu.weilnetz.de/qemu:
  tcg: Add tcg interpreter to configure / make
  tcg: Add tci disassembler
  tcg: Add interpreter for bytecode
  tcg: Add bytecode generator for tcg interpreter
  tcg: Make ARRAY_SIZE(tcg_op_defs) globally available
  tcg: TCG targets may define tcg_qemu_tb_exec
2011-11-02 20:52:13 +00:00
Richard Henderson
0756e71c3f tcg: Fix whitespace in tcg-op.h.
Removing the only tabs in the file.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: malc <av1474@comtv.ru>
2011-11-02 02:12:33 +04:00
Richard Henderson
2f98c9db0b tcg: Fix regression in tcg_gen_deposit_i64.
The error being caused by the failure to copy the other half of
the input to the output after having narrowed the deposit operation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: malc <av1474@comtv.ru>
2011-11-02 02:12:27 +04:00
Stefan Weil
7316329aa5 tcg: Add bytecode generator for tcg interpreter
Unlike other tcg target code generators, this one does not generate
machine code for some cpu. It generates machine independent bytecode
which is interpreted later.

This allows running QEMU on any host.

Interpreted bytecode is slower than direct execution of generated
machine code.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
2011-10-31 21:52:16 +01:00
Stefan Weil
2a24374ab6 tcg: Make ARRAY_SIZE(tcg_op_defs) globally available
tcg_op_defs was already a global array.

The tci disassembler also needs ARRAY_SIZE(tcg_op_defs),
so add a new global constant with this value.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
2011-10-31 21:52:16 +01:00
Stefan Weil
ce285b1754 tcg: TCG targets may define tcg_qemu_tb_exec
Targets may use a non standard definition of tcg_tb_exec
by defining this macro in their tcg_target.h.

This is used here by ppc. It will be used by the TCG interpreter, too.

Cc: malc <av1474@comtv.ru>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
2011-10-31 21:52:16 +01:00
Richard Henderson
df072774cb tcg: Optimize some forms of deposit.
If the deposit replaces the entire word, optimize to a move.

If we're inserting to the top of the word, avoid the mask of arg2
as we'll be shifting out all of the garbage and shifting in zeros.

If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit
when possible.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-30 09:06:23 +00:00
Stefan Weil
8ef935b22b tcg: Fix spelling in comment (varables -> variables)
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-14 14:39:47 +01:00
Peter Maydell
dc439de7f9 tcg/s390: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the s390 TCG backend;
this brings it into line with other backends.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-08 15:21:05 +00:00
Peter Maydell
498562926d tcg/ia64: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ia64 TCG backend;
this brings it into line with other backends.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-08 15:20:46 +00:00
Jan Kiszka
a4773324b4 tcg-i386: Introduce limited deposit support
x86 cannot provide an optimized generic deposit implementation. But at
least for a few special cases, namely for writing bits 0..7, 8..15, and
0..15, versions using only a single instruction are feasible.
Introducing such limited support improves emulating 16-bit x86 code on
x86, but also rarer cases where 32-bit or 64-bit code accesses bytes or
words.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 06:42:46 +00:00
Peter Maydell
df0eda9b73 tcg/arm: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ARM TCG backend;
this fixes a compilation failure on ARM hosts with newer gcc.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 06:15:54 +00:00
Stefan Weil
7f6f0ae5b9 tcg: Add some assertions
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 06:11:23 +00:00
Stefan Weil
c0ad3001bf tcg: Add forward declarations for local functions
These functions are defined in the tcg target specific file
tcg-target.c.

The forward declarations assert that every tcg target uses
the same function prototype.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 06:11:17 +00:00
Stefan Weil
840f58617b tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h
It is now declared for all tcg targets in tcg.h,
so the tcg target specific declarations are redundant.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 06:11:12 +00:00
Stefan Weil
817b838e3c tcg: Declare TCG_TARGET_REG_BITS in tcg.h
TCG_TARGET_REG_BITS can be determined by the compiler,
so there is no need to declare it for each individual tcg target.

This is especially important for new tcg targets
which will be supported by the tcg interpreter.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01 06:09:31 +00:00
Stefan Weil
be9c4183c4 tcg/ppc64: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.

Cc: Vassili Karpov <av1474@comtv.ru>
Fine-with-me'd-by: Vassili Karpov <av1474@comtv.ru>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:56:30 +00:00
Stefan Weil
26a74ae377 tcg/sparc: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:55:30 +00:00
Stefan Weil
5ddd17b403 tcg/s390: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.

Cc: Alexander Graf <agraf@suse.de>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:55:21 +00:00
Stefan Weil
af15a62309 tcg/ia64: Only one call output register needed for 64 bit hosts
The second register is never used for ia64 hosts.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:54:57 +00:00
Stefan Weil
68af23af69 tcg/i386: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:54:49 +00:00
Thomas Huth
e89720b116 tcg/ppc64: Fix zero extension code generation bug for ppc64 host
The ppc64 code generation backend uses an rldicr (Rotate Left Double
Immediate and Clear Right) instruction to implement zero extension of
a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64).  However
this is wrong - this instruction clears specified low bits of the
value, instead of high bits as we require for a zero extension.  It
should instead use an rldicl (Rotate Left Double Immediate and Clear
Left) instruction.

Presumably amongst other things, this causes the SLOF firmware image
used with -M pseries to not boot on a ppc64 host.

It appears this bug was exposed by commit
0bf1dbdcc9 (tcg/ppc64: fix 16/32 mixup)
which enabled the use of the op_ext32u_i64 operation on the ppc64
backend.

Signed-off-by: Thomas Huth <thuth@de.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: malc <av1474@comtv.ru>
2011-09-09 19:07:06 +04:00
Peter Maydell
70d705fd46 tcg/ppc/tcg-target.c: Avoid 'set but not used' gcc warnings
Move the declaration and initialisation of some variables in
tcg_out_qemu_ld and tcg_out_qemu_st inside CONFIG_SOFTMMU, to
avoid the "variable set but not used" warning of gcc 4.6.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: malc <av1474@comtv.ru>
2011-09-01 21:20:50 +04:00
Blue Swirl
fe0de7aa5e TCG: improve optimizer debugging
Use enum TCGOpcode instead of plain old int so that the name of
current op can be seen in GDB. Add a default case to switch
so that GCC does not complain about unhandled enum cases.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-28 07:17:27 +00:00
Richard Henderson
f412c762e2 tcg: Update --enable-debug for TCG_OPF_NOT_PRESENT.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-23 21:24:39 +02:00
malc
0bf1dbdcc9 tcg/ppc64: fix 16/32 mixup
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22 18:26:15 +04:00
malc
157f2662fb tcg/ppc64: implement not_i32/64 and ext32u_i64
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22 14:40:00 +04:00
malc
350dba6ce6 tcg/ppc32: implement deposit_i32
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22 14:39:00 +04:00
Richard Henderson
64ba39af27 tcg-ia64: Fix typos in AREG0 setup in prologue.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:26 +00:00
Richard Henderson
6e6a99249c tcg-hppa: Fix CPU_TEMP_BUF_NLONGS oversight.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:25 +00:00
Richard Henderson
cb25c80a9b tcg: Constant fold neg, andc, orc, eqv, nand, nor.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:25 +00:00
Richard Henderson
25c4d9cc84 tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.

To allow this to be checked reliably, the semantics of the
TCG_TARGET_HAS_* macros must be changed from def/undef to true/false.
This allows even more ifdefs to be removed, converting them into
C if statements.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:24 +00:00
Richard Henderson
8399ad59e7 tcg: Add and use TCG_OPF_64BIT.
This allows the simplification of the op_bits function from
tcg/optimize.c.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21 18:52:22 +00:00
Anthony Liguori
7267c0947d Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-20 23:01:08 -05:00
Blue Swirl
e31b0a7c05 TCG: fix copy propagation
Copy propagation introduced in 22613af4a6
considered only global registers. However, register temps and stack
allocated locals must be handled differently because register temps
don't survive across brcond.

Fix by propagating only within same class of temps.

Tested-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-07 09:33:20 +00:00
Blue Swirl
2ec00650f6 TCG: fix breakage by previous patch
Fix incorrect logic and typos in previous commit
1bfd07bdfe.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 18:54:23 +00:00
Blue Swirl
1bfd07bdfe TCG: fix breakage on some RISC hosts
Fix breakage by a640f03178
and 55c0975c5b.

Some TCG targets don't implement all TCG ops, so make
optimizing those conditional.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 12:21:33 +00:00
Kirill Batuzov
a640f03178 Do constant folding for unary operations.
Perform constant folding for NOT and EXT{8,16,32}{S,U} operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:30 +00:00
Kirill Batuzov
55c0975c5b Do constant folding for shift operations.
Perform constant forlding for SHR, SHL, SAR, ROTR, ROTL operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:29 +00:00
Kirill Batuzov
9a81090b12 Do constant folding for boolean operations.
Perform constant folding for AND, OR, XOR operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:29 +00:00
Kirill Batuzov
53108fb574 Do constant folding for basic arithmetic operations.
Perform actual constant folding for ADD, SUB and MUL operations.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:28 +00:00
Kirill Batuzov
22613af4a6 Add copy and constant propagation.
Make tcg_constant_folding do copy and constant propagation. It is a
preparational work before actual constant folding.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:27 +00:00
Kirill Batuzov
8f2e8c07a6 Add TCG optimizations stub
Added file tcg/optimize.c to hold TCG optimizations. Function tcg_optimize
is called from tcg_gen_code_common. It calls other functions performing
specific optimizations. Stub for constant folding was added.

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 10:51:25 +00:00
Stefan Weil
ea15fb0672 tcg/mips: Fix regression caused by typo (copy + paste bug)
cppcheck reports an error:
qemu/tcg/mips/tcg-target.c:1487: error: Invalid number of character (()

The unpatched code won't compile on mips hosts starting with commit
cea5f9a28f.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 21:03:37 +00:00
Peter Maydell
107a47cc2d tcg/README: Expand advice on number of TCG ops per target insn
Expand the note on the number of TCG ops generated per target insn,
to be clearer about the range of applicability of the 20 op rule
of thumb. Also add a note about the hard MAX_OP_PER_INSTR limit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-16 13:17:36 +00:00
Blue Swirl
f74b32dec9 TCG/PPC: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-02 18:48:28 +00:00
Richard Henderson
ec1884298c tcg-hppa: Support deposit opcode.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 21:07:28 +00:00
Blue Swirl
2a6a665f16 TCG/HPPA: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 20:52:40 +00:00
Blue Swirl
a42bceec09 TCG/HPPA: use TCG_REG_CALL_STACK instead of TCG_REG_SP
Use TCG_REG_CALL_STACK instead of TCG_REG_SP for consistency.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01 20:49:51 +00:00
malc
c24a9c6ef9 tcg/ppc64: Remove tcg_out_addi
The only user (within tcg.c) was removed

Signed-off-by: malc <av1474@comtv.ru>
2011-06-28 02:27:52 +04:00
malc
1a2eb16241 tcg/ppc: Remove tcg_out_addi
The only user (within tcg.c) was removed

Signed-off-by: malc <av1474@comtv.ru>
2011-06-28 02:26:06 +04:00
Blue Swirl
f44c99607a TCG/Sparc64: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

On Sparc64, stack pointer is not aligned but there is a fixed bias of 2047,
so don't try to enforce alignment.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:53 +00:00
Blue Swirl
ac0275dcfe TCG/x86: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG
temps.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:51 +00:00
Blue Swirl
e83c80f718 TCG/x86: use TCG_REG_CALL_STACK instead of TCG_REG_ESP
Except for specific cases where the use of %esp changes the encoding of
the instruction, it's cleaner to use TCG_REG_CALL_STACK instead of
TCG_REG_ESP.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:49 +00:00
Blue Swirl
345649c054 TCG: remove broken stack allocation for call arguments
The code for stack allocation for call arguments is way too simplistic
to actually work on targets with non-trivial stack allocation policies,
e.g. ppc64. We've also already allocated TCG_STATIC_CALL_ARGS_SIZE worth
of stack for calls which should be well more than any helper needs.

Remove broken dynamic stack allocation code and replace it with an assert.
Should dynamic stack allocation ever be needed again, target specific
functions should be added.

Thanks to Richard Henderson for the analysis.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:47 +00:00
Blue Swirl
b591dc59bc TCG: fix negative frame offset calculations
size_t is unsigned, so the frame offset calculations can be incorrect for
negative offsets.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:44 +00:00
Blue Swirl
614f104dfd Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:43 +00:00
Blue Swirl
cea5f9a28f cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.

Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue
change.

Revert the hacks to avoid AREG0 use on Sparc hosts.

Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h.

Compile the file without HELPER_CFLAGS.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:38 +00:00
Blue Swirl
2b41f10e18 Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:35 +00:00
Christophe Fergeau
568fffe353 tcg: Fix unused-but-set-variable warning
Based on a patch from Hans de Goede <hdegoede@redhat.com>

This warning is new in gcc 4.6.

Acked-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Christophe Fergeau <cfergeau@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:32:46 +02:00
Peter Maydell
ebecf36381 tcg: If DEBUG_TCGV, distinguish TCGv_ptr from TCGv_i32/TCGv_i64
When compiling with DEBUG_TCGV enabled, make the TCGv_ptr type distinct
from TCGv_i32/TCGv_i64. This means that using an i32 or i64 TCG op to
manipulate a TCGv_ptr will always be detected at compile time, rather
than only if compiling on a host system with the other word size.

NB: the tcg_add_ptr and tcg_sub_ptr macros have been removed as they
were not used anywhere.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:26:21 +02:00
Peter Maydell
6bd4b08ab2 tcg/tcg-op.h: Fix prototypes for ld/st functions on 64 bit hosts
The prototypes for the ld/st functions on a 64 bit host declared
the address parameter as a TCGv_i64 rather than a TCGv_ptr. This
worked OK (since the two are aliases), but needs to be fixed to
allow extension of TCG type debugging to i64/i32/ptr mismatches.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:26:20 +02:00
Brad
03938c133e Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD.
Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD
to fix compilation of the MIPS host support for OpenBSD/mips64 based architecures.

Signed-off-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03 18:23:53 +02:00
Stefan Weil
06ea77bc50 Fix spelling in comment (additon -> addition)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-29 11:58:28 +01:00
Aurelien Jarno
8c11ad25f4 tcg: don't keep dead outputs in registers
If an op with dead outputs is not removed, because it has side effects
or has multiple output and only one dead, mark the registers as dead
instead of saving them. This avoid a few register spills on TCG targets
with low register count, especially with div2 and mul2 ops, or when a
qemu_ld* result is not used (prefetch emulation for example).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23 22:38:26 +02:00
Aurelien Jarno
6b64b624cd tcg: mark dead output argument in op_dead_args
If an op is not removed and has dead output arguments, mark it
in op_dead_args similarly to what is done for input arguments.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23 22:38:13 +02:00
Aurelien Jarno
866cb6cb21 tcg: replace op_dead_iargs by op_dead_args
Allow all args to be dead by replacing the input specific op_dead_iargs
variable by op_dead_args. Note this is a purely mechanical change.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23 22:38:11 +02:00
Stefan Weil
5225d66921 Fix typos in comments (accross -> across)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-08 10:02:16 +01:00
Peter Maydell
24e838b787 tcg/arm: Support host code being compiled for Thumb
Although the TCG generated code is always in ARM mode, it is possible
that the host code was compiled by gcc in Thumb mode (this is often the
default for Linux distributions targeting ARM v7 only). Handle this
by using BLX imm when doing a call from ARM into Thumb mode.
Since BLX imm is not a conditionalisable instruction, we make
tcg_out_call() no longer take a condition code; we were only ever
using it with COND_AL anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-24 03:27:22 +01:00
Peter Maydell
27bfd83c33 tcg: Add support for debugging leakage of temporaries
Add support (if CONFIG_DEBUG_TCG is defined) for debugging leakage
of temporary variables. Generally any temporaries created by
a target while it is translating an instruction should be freed
by the end of that instruction; otherwise carefully crafted
guest code could cause TCG to run out of temporaries and assert.
By calling tcg_check_temp_count() after each instruction we can
check that we are not leaking temporaries in this way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07 09:26:06 +01:00
Edgar E. Iglesias
3a34dfd7f6 tcg: README, name deposit second argument len/LEN
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-20 12:16:57 +01:00
Richard Henderson
b7767f0f3c tcg: Define "deposit" as an optional operation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-20 12:16:05 +01:00
Aurelien Jarno
5677903453 tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that people
developping new targets based on existing ones are warned of the issue.

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12 00:06:07 +01:00
Aurelien Jarno
0f11f25a00 tcg/arm: improve constant loading
Improve constant loading in two ways:
- On all ARM versions, it's possible to load 0xffffff00 = -0x100 using
  the mvn rd, #0. Fix the conditions.
- On <= ARMv6 versions, where movw and movt are not available, load the
  constants using mov and orr with rotations depending on the constant
  to load. This is very useful for example to load constants where the
  low byte is 0. This reduce the generated code size by about 7%.

Also fix the coding style at the same time.

Cc: Andrzej Zaborowski <balrog@zabor.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10 07:30:30 +01:00
Aurelien Jarno
a3e28aa5c7 tcg/ia64: remove an unnecessary stop bit
Spotted by Richard Henderson.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10 01:39:49 +01:00
Mike Frysinger
759c90ba3d tcg: fix typo in readme
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-09 21:01:01 +00:00
Stefan Weil
aa95e3a57f tcg/README: Spelling fixes
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-09 21:00:16 +00:00
Aurelien Jarno
d43ffce140 tcg/mips: fix branch target change during code retranslation
TCG on MIPS was trying to avoid changing the branch offset, but didn't
due to a stupid typo. Fix it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:41:43 +01:00
Aurelien Jarno
9a3abc21a6 tcg/arm: fix qemu_st64 for big endian targets
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of
a 64 bit word before saving it. This patch fixes that.

Acked-by: Andrzej Zaborowski <balrogg@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:41:33 +01:00
Aurelien Jarno
c69806ab82 tcg/arm: fix branch target change during code retranslation
QEMU uses code retranslation to restore the CPU state when an exception
happens. For it to work the retranslation must not modify the generated
code. This is what is currently implemented in ARM TCG.

However on CPU that don't have icache/dcache/memory synchronised like
ARM, this requirement is stronger and code retranslation must not modify
the generated code "atomically", as the cache line might be flushed
at any moment (interrupt, exception, task switching), even if not
triggered by QEMU. The probability for this to happen is very low, and
depends on cache size and associativiy, machine load, interrupts, so the
symptoms are might happen randomly.

This requirement is currently not followed in tcg/arm, for the
load/store code, which basically has the following structure:
  1) tlb access code is written
  2) conditional fast path code is written
  3) branch is written with a temporary target
  4) slow path code is written
  5) branch target is updated
The cache lines corresponding to the retranslated code is not flushed
after code retranslation as the generated code is supposed to be the
same. However if the cache line corresponding to the branch instruction
is flushed between step 3 and 5, and is not flushed again before the
code is executed again, the branch target is wrong. In the guest, the
symptoms are MMU page fault at a random addresses, which leads to
kernel page fault or segmentation faults.

The patch fixes this issue by avoiding writing the branch target until
it is known, that is by writing only the branch instruction first, and
later only the offset.

This fixes booting linux guests on ARM hosts (tested: arm, i386, mips,
mipsel, sh4, sparc).

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08 16:39:47 +01:00
Richard Henderson
393f398b69 tcg-ia64: Fix warning in qemu_ld.
The usermode version of qemu_ld doesn't used mem_index,
leading to set-but-not-used warnings.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
07f59737d8 tcg-ia64: Fix address compilation in qemu_st.
A typo in the usermode address calculation path; R3 used where R2 needed.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
650a217a65 tcg-ia64: Fix tlb read error for 32-bit targets.
Use ld4 not ld8 for reading the tlb of 32-bit targets.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
b3b0091f07 tcg-ia64: Implement qemu_ld32.
The port was not properly merged following
86feb1c860

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
255108c0e3 tcg-ia64: Provide default GUEST_BASE.
Fix compilation error when GUEST_BASE is not defined.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:31 +01:00
Richard Henderson
0909cbde9a tcg: Fix default definition of divu_i32 and remu_i32.
The arguments to tcg_gen_helper32 for these functions were not
updated correctly in rev 2bece2c883.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01 19:48:30 +01:00
Stefan Weil
405cf9ff00 tcg: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:58 +00:00
Stefan Weil
c3b08d0e05 tcg: Fix compiler error (comparison of unsigned expression)
When qemu is configured with --enable-debug-tcg,
gcc throws this warning (or error with -Werror):

tcg/tcg.c:1030: error: comparison of unsigned expression >= 0 is always true

Fix it by removing the >= 0 part.
The type cast to 'unsigned' catches negative values of op
(which should never happen).

This is a modification of Hollis Blanchard's patch.

Cc: Hollis Blanchard <hollis@penguinppc.org>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-20 20:52:12 +00:00
Andreas Färber
b1d6d51d95 TCG: Revert ppc64 tcg_out_movi32 change
3b6dac3416 apparently broke the ppc64 TCG target
compilation in the code path without guest base.

Reverting this line fixes the build.

Signed-off-by: Andreas F?rber <andreas.faerber@web.de>
Cc: malc <av1474@comtv.ru>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: malc <av1474@comtv.ru>
2010-08-15 00:57:40 +04:00
Andreas Färber
e9119cd864 TCG: Fix Darwin/ppc calling convention recognition
5da79c86a3 broke compilation on Mac OS X v10.5 ppc.
Apple's GCC 4.0.1 does not define _CALL_DARWIN. Recognize __APPLE__ again as well.

Signed-off-by: Andreas F?rber <andreas.faerber@web.de>
Cc: malc <av1474@comtv.ru>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: J?rgen Lock <nox@jelal.kn-bremen.de>
Cc: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: malc <av1474@comtv.ru>
2010-08-15 00:40:42 +04:00
Richard Henderson
48bb3750e1 tcg-s390: new TCG Target
Original patch from Ulrich Hecht, further work from Alexander Graf
and Richard Henderson.

Cc: Ulrich Hecht <uli@suse.de>
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29 23:07:51 +02:00
Richard Henderson
b9e946c781 tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.
We need not reserve the register unless we're going to use it.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: malc <av1474@comtv.ru>
2010-06-29 23:30:36 +04:00
Richard Henderson
2bece2c883 tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments.  Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be
zero-extended to 64-bits.

To effect this, extend the "sizemask" parameter to tcg_gen_callN
to include the signedness of the type of each parameter.  If the
tcg target requires it, extend each 32-bit argument into a 64-bit
temp and pass that to the function call.

This ABI feature is required by sparc64, ppc64 and s390x.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-16 11:29:11 +02:00
Aurelien Jarno
0e2029a063 tcg: fix DEF macro after commit c61aaf7a38
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11 18:39:47 +02:00
Richard Henderson
1bcaae666f tcg-s390: Icache flush is a no-op.
Before gcc 4.2, __builtin___clear_cache doesn't exist, and
afterward the gcc s390 backend implements it as nothing.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11 08:46:05 +02:00
Aurelien Jarno
dc397ca35e tcg-i386: fix andi r, r, 0xff
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10 20:52:47 +02:00
Aurelien Jarno
447d681e8b tcg-i386: remove use of _Bool that slipped code review
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10 20:41:08 +02:00
Richard Henderson
5d8a4f8f4a tcg-i386: Merge 64-bit generation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10 00:16:21 +02:00
Aurelien Jarno
c61aaf7a38 tcg: get rid of DEF2 in tcg-opc.h
Now that tcg-opc.h is only used in TCG code, get rid of DEF2 in
tcg-opc.h.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Aurelien Jarno
239fda311a tcg: get rid of copy_size in TCGOpDef
copy_size is a left-over from the dyngen era, remove it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Richard Henderson
e4d58b41f9 tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:26 +02:00
Richard Henderson
3b6dac3416 tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter.  This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"
as represented by the existing TCG_TYPE_PTR.

Update all targets to match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 11:18:25 +02:00
Aurelien Jarno
4309a79bff tcg-i386: fix a typo
Fix a typo introduced by c28b14c694.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-03 00:02:30 +02:00
Aurelien Jarno
c28b14c694 tcg-i386: declare tcg_out_tlb_load() inline
Declare tcg_out_tlb_load() inline so that we don't loose optimisations
with commit 8516a04467.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:51:06 +02:00
Richard Henderson
82bb07db0c tcg-i386: Remove some ifdefs in qemu_ld/st.
Tidy some code by replacing ifdefs by C ifs.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:27 +02:00
Richard Henderson
8516a04467 tcg-i386: Split out tlb load function.
Share some code between qemu_ld and qemu_st.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
1a6dc1e406 tcg-i386: Swap order of TLB hit and miss paths.
Make fallthru be TLB hit and branch be TLB miss.  Doing this
both improves branch prediction and will allow further cleanup.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
be5a4eb7f0 tcg-i386: Split out TLB Hit path from qemu_ld/st.
Splitting out these functions will allow further cleanups.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
96b4cf38f0 tcg-i386: Tidy data16 prefixes.
Include it in the opcode as an extension, as with P_EXT
or the REX bits in the x86-64 port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02 22:50:26 +02:00
Richard Henderson
3e1dbaddbf tcg: Use INDEX_op_qemu_ld32 for 32-bit results.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-28 20:54:34 +02:00
Richard Henderson
6781d08d2e tcg-ia64: Load GUEST_BASE into a register.
Saves one bundle per memory operation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
7221f058a6 tcg-ia64: Fix some register usage issues.
(1) The output registers were not marked call-clobbered, even though
    they can be modified by called functions.
(2) The thread pointer was not marked reserved.
(3) R4-R6 are call-saved, but not saved by the prologue.  Rather than
    save them, mark them reserved so that we don't use them.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
4b31713dc4 tcg-hppa: Load GUEST_BASE as an immediate.
Now that the prologue is generated after GUEST_BASE is fixed,
we can load it as an immediate, and also avoid reserving the
register if it isn't necessary.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
9002ec794e tcg: Initialize the prologue after GUEST_BASE is fixed.
This will allow backends to make intelligent choices about how
to implement GUEST_BASE.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 18:41:21 +02:00
Richard Henderson
7868652357 tcg-i386: Nuke trailing whitespace.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:23 +00:00
Richard Henderson
5d1e4e85ce tcg-i386: Use lea for three-operand add.
The result is shorter than the mov+add that TCG would
otherwise generate for us.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:23 +00:00
Richard Henderson
34a6d0b7fc tcg-i386: Tidy lea.
Implement full modrm+sib addressing mode processing.
Use that in qemu_ld/st to output the LEA.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
b3e66df71a tcg-i386: Tidy xchg.
Define and use OPC_XCHG_ax_r32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
0566d38737 tcg-i386: Tidy multiply.
Define and use OPC_IMUL_GvEv{,Ib,Iz}.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
9363dedbbb tcg-i386: Tidy unary arithmetic.
Define OPC_GRP3 and EXT3_FOO to match.  Use them instead of
bare constants.

Define OPC_GRP5 and rename the existing EXT_BAR to EXT5_BAR to
make it clear which extension should be used with which opcode.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
32a8ffb970 tcg-i386: Tidy setcc.
Define and use OPC_SETCC.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
3c3accc670 tcg-i386: Tidy ret.
Define and use OPC_RET.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
aadb21a4b2 tcg-i386: Tidy calls.
Define OPC_CALL_Jz, generated by tcg_out_calli; use the later
throughout.  Unify the calls within qemu_st; adjust the stack
with a single pop if applicable.

Define and use EXT_CALLN_Ev for indirect calls.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
6858614e6c tcg-i386: Tidy push/pop.
Move tcg_out_push/pop up in the file so that they can be used
by qemu_ld/st.  Define a tcg_out_pushi to be used as well.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
ef10b106b6 tcg-i386: Tidy movi.
Define and use OPC_MOVL_Iv.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
81570a70a0 tcg-i386: Tidy non-immediate arithmetic operations.
Add more OPC values, and tgen_arithr.  Use the later throughout.

Note that normal reg/reg arithmetic now uses the Gv,Ev opcode form
instead of the Ev,Gv opcode form used previously.  Both forms
disassemble properly, and so there's no visible change when diffing
log files before and after the change.  This change makes the operand
ordering within the output routines more natural, and avoids the need
to define an OPC_ARITH_EvGv since a read-modify-write with memory is
not needed within TCG.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
a369a702a1 tcg-i386: Tidy immediate arithmetic operations.
Define OPC_ARITH_EvI[bz]; use throughout.  Use tcg_out_ext8u
directly in setcond.  Use tgen_arithi in qemu_ld/st.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
6817c35598 tcg-i386: Tidy ext8s and ext16s operations.
Define OPC_MOVSBL and OPC_MOVSWL.  Factor opcode emission to
separate functions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
55e082a7a5 tcg-i386: Tidy ext8u and ext16u operations.
Define OPC_MOVZBL and OPC_MOVZWL.  Factor opcode emission to
separate functions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21 16:20:22 +00:00
Richard Henderson
da441cffde tcg-i386: Tidy jumps.
Define OPC_JCC*, OC_JMP*, and EXT_JMPN_Ev.  Use them throughout.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-20 21:15:25 +02:00
Richard Henderson
a042ef9470 tcg-i386: Eliminate extra move from qemu_ld64.
If the address register overlaps one of the output registers
simply issue the clobbering load last, rather than emitting
an extra move of the address register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-20 21:15:09 +02:00
Richard Henderson
af2660894f tcg-i386: Tidy move operations.
Define OPC_MOVB* and OPC_MOVL*; use them throughout.
Use tcg_out_ld/st instead of bare tcg_out_modrm_offset
when it makes sense.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-20 21:13:43 +02:00
Richard Henderson
f53dba0101 tcg-i386: Tidy shift operations.
Define OPC_SHIFT_{1,Ib,cl}.  Factor opcode emission to a function.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-20 21:09:08 +02:00
Richard Henderson
fcb5dac1f7 tcg-i386: Tidy bswap operations.
Define OPC_BSWAP.  Factor opcode emission to separate functions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-20 21:04:47 +02:00
Richard Henderson
4ab50ccf61 tcg-i386: Tidy initialization of tcg_target_call_clobber_regs.
Setting the registers one by one is easier to read, and gets
optimized by the compiler just the same.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-19 08:46:10 +02:00
Richard Henderson
6648e29608 tcg-i386: Allocate call-saved registers first.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-19 08:46:10 +02:00
Stefan Weil
a5ad59166a tcg: Add missing 'static' attribute
tcg_out_reloc is only used locally (in */target.c which is
included in tcg.c).

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-07 17:53:05 +00:00
Richard Henderson
70ec48ef55 tcg-hppa: Remove automatically implemented opcodes.
Remove neg, ext8u, ext16u, as requested.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-26 20:06:18 +02:00
Richard Henderson
2d097a83e2 tcg-hppa: Fix branch offset during retranslation.
Branch offsets should only be overwritten during relocation,
to support partial retranslation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-26 20:06:17 +02:00
Richard Henderson
739734cb5c tcg-hppa: Schedule the address masking after the TLB load.
Issue the tlb load as early as possible and perform the address
masking while the load is completing.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-26 20:06:17 +02:00
Richard Henderson
f061b40e91 tcg-hppa: Fix softmmu loads and stores.
Along the tlb hit path, we were modifying the variables holding the input
register numbers, which lead to incorrect expansion of the tlb miss path.
Fix this by extracting the tlb hit path to separate functions with their
own local variables.  This also makes the difference between softmmu and
user-only easier to read.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-26 20:06:17 +02:00
Richard Henderson
884d348b7b tcg-hppa: Fix GUEST_BASE initialization in prologue.
Load from the guest_base variable rather than embed a constant.
Always reserve TCG_GUEST_BASE_REG if guest base support enabled.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-26 20:06:17 +02:00
Richard Henderson
0085bd5161 tcg-hppa: Constrain immediate inputs to and_i32, or_i32, andc_i32.
Define "M" constraint for and_mask_p and "O" constraint for or_mask_p.
Assume that inputs are correct in tcg_out_ori and tcg_out_andi.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-26 20:06:17 +02:00
Blue Swirl
9678d9501b Remove dead assignments in various common files, spotted by clang analyzer
Value stored is never read.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-25 18:35:52 +00:00
Aurelien Jarno
e23886a91d tcg/arm: fix condition in zero/sign extension functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-25 05:46:22 +02:00
Aurelien Jarno
c66b5c2cb6 tcg/arm: don't try to load constants using pc
There is statistically almost 0 chances to use this code, so
remove it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
914ccf51b0 tcg/arm: optimize register allocation order
The beginning of the register allocation order list on the TCG arm
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
bf5675efe3 tcg/arm: fix argument alignment in qemu_st64
64-bit arguments should be aligned on an even register as specified
by the "Procedure Call Standard for the ARM Architecture".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
2633a2d015 tcg/arm: remove useless register tests in qemu_ld/st
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the
constraints. Don't check if they equals these registers.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
67dcab7327 tcg/arm: bswap arguments in qemu_ld/st if needed
On big endian targets, data arguments of qemu_ld/st ops have to be
byte swapped. Two temporary registers are needed for qemu_st to do
the bswap. r0 and r1 are used in system mode, do the same in user
mode, which implies reworking the constraints.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
e854b6d39c tcg/arm: use ext* ops in qemu_ld
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
7e0d95628d tcg/arm: remove conditional argument for qemu_ld/st
While it make sense to pass a conditional argument to tcg_out_*()
functions as the ARM architecture allows that, it doesn't make sense
for qemu_ld/st functions. These functions use comparison instructions
and conditional execution already, so it is not possible to use a
second level of conditional execution.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:06 +02:00
Aurelien Jarno
244b1e81f6 tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16
instructions on ARMv6+ or shifts and logical operations on previous
ARM versions. In both cases the result use less instructions than
the pure TCG version.

These ops are also needed by the qemu_ld/st functions.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
9517094f72 tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or two
shifts on previous ARM versions. In both cases the result use the same
number or less instructions than the pure TCG version.

Also move all sign extension code to separate functions, so that they
can be reused in other parts of the code.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
293579e55c tcg/arm: add rotation ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
23401b58a4 tcg/arm: use the blx instruction when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
8f7f749f21 tcg/arm: sxtb and sxth are available starting with ARMv6
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:03:02 +02:00
Aurelien Jarno
ac34fb5c5d tcg/arm: add variables to define the allowed instructions set
Use a set of variables to define the allowed ARM instructions, depending
on the __ARM_ARCH_*__ GCC defines.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
2488b41bb2 tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
c8d80cef55 tcg/arm: replace integer values by registers enum
The TCG ARM backends uses integer values to refer to both immediate
values and register number. This makes the code difficult to read.

The patch below replaces all (if I haven't miss any ;-) integer values
representing register number by TCG_REG_* enum values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
f694a27ed7 tcg/arm: remove store signed functions
Store signed functions doesn't make sense, and are not used. Remove
them.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
e4a7d5e88c tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that are
clobbered or reserved one by one. This makes the code easier to read.

Also declare all the 16 registers to TCG, and mark pc as reserved.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
Aurelien Jarno
39221a82be tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to a
subroutine. According to the "Procedure Call Standard for the ARM
Architecture", it is the job of the callee to save this register.
Moreover, this register is already saved in the prologue/epilogue.

This patch removes the disabled SAVE_LR code, as there is no need to
reenable later.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19 07:02:53 +02:00
malc
606257c6f2 tcg/ppc: Remove redundant comparison from brcond2
Signed-off-by: malc <av1474@comtv.ru>
2010-04-18 08:46:29 +04:00
Richard Henderson
2d8ebcf94e Fix --enable-profiler compilation.
There's a header file inclusion ordering problem between cpu-all.h
and qemu-timer.h, such that cpu_get_real_ticks is not defined when
we attempt to use it in profile_getclock.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-17 16:25:10 +00:00
malc
655feed5d9 tcg: Add missing static qualifier
Build breaks otherwise when USE_LIVENESS_ANALYSIS is not defined.

Signed-off-by: malc <av1474@comtv.ru>
2010-04-17 08:00:41 +04:00
malc
efe72c8de7 tcg/ppc: Fix signed versions of brcond2
Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.

Signed-off-by: malc <av1474@comtv.ru>
2010-04-17 08:00:32 +04:00
Stefan Weil
60bf84cf4c tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilations
without optimisation, because the compiler makes heavy use
of this register (so the resulting code crashes).

Register s0 had been used for TCG_AREG1 in earlier releases,
but was no longer used and is now free for TCG_AREG0.

The resulting code works for compilations without
optimisation (tested with qemu mips in qemu mips
on x86 host).

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-14 00:59:42 +02:00
Aurelien Jarno
837d987bb9 tcg/README: improve description of bswap*
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-10 03:36:21 +02:00
Richard Henderson
3e1f46eaa4 tcg-hppa: Don't try to calls to non-constant addresses.
PA-RISC uses procedure descriptors.  We'd need to emit a call to
the millicode routine $$dyncall.  However, this situation doesn't
actually arise, since we always have the descriptor available at
TCG code generation time.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:57:16 +02:00
Richard Henderson
91493631fe tcg-hppa: Fix in/out register overlap in add2/sub2.
Handle the output log part overlapping the input high parts.
Also, improve sub2 to handle some constants the second input low part.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:57:14 +02:00
Richard Henderson
fd76e73a10 tcg-hppa: Finish the port.
Delete inline functions from tcg-target.h that don't need to be there,
move the others to tcg-target.c.  Add 'Z', 'I', 'J' constraints for
0, signed 11-bit, and signed 5-bit respectively.  Add GUEST_BASE support
similar to ppc64, with the value stored in a register.  Add missing
registers to reg_alloc_order.  Add support for 12-bit branch relocations.
Add functions for synthetic operations: addi, mtctl, dep, shd, vshd, ori,
andi, shifts, rotates, multiply, branches, setcond.  Split out TLB reads
from qemu_ld and qemu_st; fix argument loading for tlb external calls.
Generate the prologue.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
Aurelien Jarno
a175b996b2 tcg/ia64: fix tlb addend read
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
malc
98926b0a25 tcg/ppc64: Fix typo
Signed-off-by: malc <av1474@comtv.ru>
2010-04-07 02:26:22 +04:00
malc
f7e2aca834 tcg/ppc: Fix typo
Signed-off-by: malc <av1474@comtv.ru>
2010-04-06 03:10:03 +04:00
malc
a884dcb804 tcg/ppc: Implment bswap16/32
Signed-off-by: malc <av1474@comtv.ru>
2010-04-06 02:54:22 +04:00
Aurelien Jarno
116348def2 tcg/mips: use seb/seh instructions on MIPS32R2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05 15:16:44 +02:00
Aurelien Jarno
ba0d89bbeb tcg/mips: fix 64-bit linux-user on big endian MIPS
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05 15:16:44 +02:00
malc
aa77bebd98 tcg/ppc: Implement eqv, nand and nor
Signed-off-by: malc <av1474@comtv.ru>
2010-04-05 16:09:05 +04:00
Paul Brook
355b194369 Split TLB addend and target_phys_addr_t
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t).  However since the introduction of
the iotlb field it has only been used for RAM accesses.

This means we can change the type of addend to unsigned long, and remove
associated hacks in the big-endian TCG backends.

We can also remove the host dependence from target_phys_addr_t.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05 00:28:53 +01:00
malc
36368cf0d5 tcg/ppc: Fix not_i32
Thanks to Alexander Graf for bug report and a good reproducible test
case.

Signed-off-by: malc <av1474@comtv.ru>
2010-04-04 20:36:29 +04:00
Aurelien Jarno
a18f844fb5 tcg/TODO: remove setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-01 22:00:41 +02:00