Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This change is needed because commit 06e12b65
now uses an unsigned long long value
(uint64_t && unsigned long long => unsigned long long).
Cc: Tsuneo Saito <tsnsaito@gmail.com>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This patch implements MMU faults caused by TTE.NFO and TTE.E:
- access other than nonfaulting load to a page marked NFO should
raise data_access_exception
- nonfaulting load to a page marked with E bit should raise
data_access_exception
To distinguish nonfaulting loads, this patch extends (abuses?) the rw
argument of get_physical_address_data(). rw is set to 4 on nonfaulting
loads.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu_get_phys_page_nofault() calls get_physical_address() twice,
that results in overwriting the fault status in the SFSR.
We need this change in order for nonfaulting loads to raising MMU faults
as normal loads do.
Also removed the call to cpu_get_physical_page_desc() since we are
going to modify nonfaulting loads raising MMU faults.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This patch makes cpu_get_phys_page_debug() independent from
cpu_get_phys_page_nofault() in advance of implementing nonfaulting load.
This also modifies cpu_get_phys_page_nofault() to be compiled only on
TARGET_SPARC64 because it is not required on SPARC32.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Introduce cpu_sparc_get_phys_page() to be used as a help for splitting
cpu_get_phys_page_debug() from cpu_get_phys_page_nofault().
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Add macros for SFSR fields and use macros instead of magic numbers.
Also fix the update of the register fields on MMU faults.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Add macros for TTE bits and modify to use macros instead of
magic numbers.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
do_interrupt() was mixing CPUState pointer passed from caller
and global env (AREG0).
Fix by moving the function to helper.c. Introduce a helper for calling
change_pstate() safely from outside of execution context.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This patch removes all references to signal.h when qemu-common.h is included
as they become redundant.
Signed-off-by: Alexandre Raymond <cerbere@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
The "leon3_cache_control_int" (op_helper.c) function is called within leon3.c
which leads to segfault error with the global "env".
Now cache control is a CPU feature and everything is handled in op_helper.c.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This register is activated by CPU_FEATURE_ASR17 in the feature field.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more
information on http://www.gaisler.com).
Leon3 is made of multiple components available in the GrLib VHDL library.
Three devices are implemented: uart, timers and IRQ manager.
You can find code for these peripherals in the grlib_* files.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
fprintf_function uses format checking with GCC_FMT_ATTR.
Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- set mmu tag access register on FAULT and PROT traps as well
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero
- cpu_get_tb_cpu_state: store trap level and primary context in flags
this allows to restart code translation when address translation is changed
- stop translation block after writing to pstate and tl registers
- stop translation block after writing to alternate space
this can be optimized to stop only if address translation can be changed
by write operation (e.g. by comparing with MMU ASI values)
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- refactor code to handle hpstate only if available for current cpu
- conditionally set hypervisor bit in hpstate register
- reorder softmmu indices so user accessable ones go first, translation context
macros supervisor() and hypervisor() adjusted as well
- disable sparcv8 registers for TARGET_SPARC64
- fix cpu_mmu_index to use sparcv9 bits only
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- separate PRIV and PROT handling
- DPRINTF_MMU macro to clean up debug code
- dump mmu_idx, trap level and mmu context registers
along with address translation values
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu_get_ccr() returns a target_ulong, so a type cast is needed to avoid
wrong output on big endian hosts. We could also use TARGET_FMT_lx,
but that would print 8 instead of 2 digits.
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier
flags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actual
functions to op_helper.c.
Thanks to Igor Kovalenko for reporting.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix errors missed in 2065061ede:
CC sparc64-softmmu/helper.o
cc1: warnings being treated as errors
/src/qemu/target-sparc/helper.c: In function 'get_physical_address':
/src/qemu/target-sparc/helper.c:426: warning: 'context' may be used uninitialized in this function
/src/qemu/target-sparc/helper.c:426: note: 'context' was declared here
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- increase max supported MMU modes to 6
- handle nucleus context asi
- handle secondary context asi
- handle non-faulting loads from secondary context
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- match global tte against any context
- show global tte in MMU dump
v0->v1: added default case to switch statement in demap_tlb
- should fix gcc warning about uninitialized context variable
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page. However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.
Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages. If the guest invalidates this region then flush the
whole TLB.
Signed-off-by: Paul Brook <paul@codesourcery.com>
if the access check fails, the page can not be modified
and shouldn't be marked dirty.
The patch fixes the "hsfs_putpage: dirty HSFS page"
error in Solaris guests.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Common:
* Remove unnecessary 0x prefix
* Print %y
* Fix NZVC flag print order to match CPU bit order
Sparc64 specific:
* Print registers without line wrapping
* Print %f40-%f63
* Pretty print CCR flags
* Print %fsr and %fprs in full precision
* More consistent formatting
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding
trap level.
This patch removes tsptr from sparc64 cpu state and replaces
all uses with call to helper routine.
Changes v0->v1:
- reimplemented helper routine with tcg generator
- on cpu reset trap type and pstate are populated with power-on reset
values, including tl=maxtl
Signed-off-by: igor.v.kovalenko@gmail.com
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- implement "used" bit in tlb translation entry
- mark tlb entry used if qemu code/data translation succeeds
- fold i/d mmu replacement writes code into replace_tlb_1bit_lru which
adds 1bit lru replacement algorithm; previously code tried to replace
first unlocked entry only
- extract more bitmasks to named macros
- add "immu" or "dmmu" type name to debugging output where appropriate
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
- add names to mmu registers, this helps understanding the code which
uses/modifies them.
- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries
- extract demap_tlb routine (code duplication)
- extract replace_tlb routine (code duplication)
- flush qemu tlb translations when replacing sparc64 mmu tlb entries
I have no test case which demands flushing qemu translations,
and this patch should have no other visible changes to runtime.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
I used the following command to enable debugging:
perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/*
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>> Good trap handling is required to process interrupts.
>> This patch fixes the following:
>>
>> - sparc64 has no wim register
>> - sparc64 has no psret register, use IE bit of pstate
>> extract IE checking code to cpu_interrupts_enabled
>> - alternate globals are not available if cpu has GL feature
>> in this case bit AG of pstate is constant zero
>> - write to pstate must actually write pstate
>> even if cpu has GL feature
>>
>> Also timer interrupt is handled using do_interrupt.
>
> A bit too much for one patch. Please also remove the code instead of
> commenting out.
I now excluded timer interrupt related part.
To my mind other changes are essentially tied together.
> PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.
Fixed, please find attached the updated version.
--
Kind regards,
Igor V. Kovalenko
This patch extracts common part of sparc64 tag
matching code used by IMMU and DMMU lookups.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
This Implement physical address truncation in mmu bypass mode.
IMMU bypass is also active when cpu enters RED_STATE
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
