Commit Graph

87838 Commits

Author SHA1 Message Date
Bin Meng
2cc04550ac hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
Since commit 78da6a1bca ("device_tree: add qemu_fdt_setprop_string_array helper"),
we can use the new helper to set the compatible strings for the
SiFive test device node.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08 09:59:42 +10:00
Bin Meng
cb53b283b5 hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
Since commit 78da6a1bca ("device_tree: add qemu_fdt_setprop_string_array helper"),
we can use the new helper to set the clock name for the ethernet
controller node.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08 09:59:41 +10:00
Peter Maydell
33ba8b0adc Trivial branch pull request 20210607
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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging

Trivial branch pull request 20210607

# gpg: Signature made Mon 07 Jun 2021 19:56:43 BST
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-branch-for-6.1-pull-request:
  vhost-vdpa: Remove redundant declaration of address_space_memory
  scripts/oss-fuzz: Fix typo in documentation
  target/mips: Fix 'Uncoditional' typo
  target/hppa: Remove unused 'memory.h' header
  hw/display/macfb: Classify the "nubus-macfb" as display device
  target/nios2: fix page-fit instruction count
  docs: fix broken reference
  linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[]
  misc: Correct relative include path
  i386/kvm: The value passed to strerror should be positive
  target/riscv: Do not include 'pmp.h' in user emulation

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-07 20:05:29 +01:00
Peter Maydell
a35947f15c A few testing and configure updates:
- add the multiarch signals stress test
   - fix display of multi-word compiler stanzas in meson
   - fix quoting of multi-word compiler stazas in configure.sh
   - tag some acceptance tests as TCG only
   - make checkpatch test work harder to find clean diffs
   - split gprof/gconv job to avoid timeouts
   - fix centos8 VM build by adding --source-path
   - make checkpatch aware of .h.inc and .c.inc paths
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Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging

A few testing and configure updates:

  - add the multiarch signals stress test
  - fix display of multi-word compiler stanzas in meson
  - fix quoting of multi-word compiler stazas in configure.sh
  - tag some acceptance tests as TCG only
  - make checkpatch test work harder to find clean diffs
  - split gprof/gconv job to avoid timeouts
  - fix centos8 VM build by adding --source-path
  - make checkpatch aware of .h.inc and .c.inc paths

# gpg: Signature made Mon 07 Jun 2021 14:51:12 BST
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-testing-updates-070621-2:
  scripts/checkpatch.pl: process .c.inc and .h.inc files as C source
  tests/vm: expose --source-path to scripts to find extra files
  gitlab-ci: Split gprof-gcov job
  gitlab: work harder to avoid false positives in checkpatch
  tests/acceptance: tag various arm tests as TCG only
  tests/tcg/configure.sh: tweak quoting of target_compiler
  meson.build: fix cosmetics of compiler display
  tests/tcg: add a multiarch signals test to stress test signal delivery

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-07 15:45:48 +01:00
Matheus Ferst
72205289a0 scripts/checkpatch.pl: process .c.inc and .h.inc files as C source
Change the regex used to determine whether a file should be processed as
C source to include .c.inc and .h.inc extensions.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Message-Id: <20210520195142.941261-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-06-07 14:49:30 +01:00
Alex Bennée
7bb17a9263 tests/vm: expose --source-path to scripts to find extra files
Currently the centos8 image expects to run an in-src build to find the
kick starter file. Fix this.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210602103527.32021-1-alex.bennee@linaro.org>
2021-06-07 14:42:47 +01:00
Philippe Mathieu-Daudé
e2d3017809 gitlab-ci: Split gprof-gcov job
This job is hitting the 70min limit, so split it in 2 tasks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <20210525082556.4011380-7-f4bug@amsat.org>
2021-06-07 14:42:47 +01:00
Alex Bennée
b114a0b943 gitlab: work harder to avoid false positives in checkpatch
This copies the behaviour of patchew's configuration to make the diff
algorithm generate a minimal diff.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-Id: <20210602153247.27651-1-alex.bennee@linaro.org>
2021-06-07 14:42:47 +01:00
Alex Bennée
e2ff831462 tests/acceptance: tag various arm tests as TCG only
We should never be trying to run most of these models under a KVM
environment.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <20210527160319.19834-7-alex.bennee@linaro.org>
2021-06-07 14:42:47 +01:00
Alex Bennée
31fa83bd2b tests/tcg/configure.sh: tweak quoting of target_compiler
If you configure the host compiler with a multi-command stanza like:

  --cc="ccache gcc"

then the configure.sh machinery falls over with confusion. Work around
this by ensuring we correctly quote so where we need a complete
evaluation we get it. Of course the has() check needs single variable
so we need to unquote that. This does mean it essentially checks that
just the ccache command exits but if we got past that step we still
check the compiler actually does something.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Message-Id: <20210527160319.19834-4-alex.bennee@linaro.org>
2021-06-07 14:42:47 +01:00
Alex Bennée
63de93530f meson.build: fix cosmetics of compiler display
If you specify something like --cc="ccache gcc" on your configure line
the summary output misses the rest of the cmd_array. Do some string
joining to make it complete.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210527160319.19834-3-alex.bennee@linaro.org>
2021-06-07 14:42:47 +01:00
Alex Bennée
81c4edc39e tests/tcg: add a multiarch signals test to stress test signal delivery
This adds a simple signal test that combines the POSIX timer_create
with signal delivery across multiple threads. The aim is to provide a
bit more of a stress test to flush out signal handling issues for
easily than the occasional random crash we sometimes see in linux-test
or threadcount.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210527160319.19834-2-alex.bennee@linaro.org>
2021-06-07 14:42:42 +01:00
Xie Yongji
df77d45a51 vhost-vdpa: Remove redundant declaration of address_space_memory
The symbol address_space_memory are already declared in
include/exec/address-spaces.h. So let's add this header file
and remove the redundant declaration in include/hw/virtio/vhost-vdpa.h.

Signed-off-by: Xie Yongji <xieyongji@bytedance.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20210517123246.999-1-xieyongji@bytedance.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:33:46 +02:00
Philippe Mathieu-Daudé
eeae5466c4 scripts/oss-fuzz: Fix typo in documentation
While we only use stdin, the chardev is named 'stdio'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20210602170759.2500248-4-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:29:39 +02:00
Philippe Mathieu-Daudé
6397856019 target/mips: Fix 'Uncoditional' typo
Fix Uncoditional -> Unconditional typo.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Message-Id: <20210602170759.2500248-3-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:28:54 +02:00
Philippe Mathieu-Daudé
8daec64be9 target/hppa: Remove unused 'memory.h' header
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517101558.1040191-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:23:14 +02:00
Thomas Huth
69b66e4977 hw/display/macfb: Classify the "nubus-macfb" as display device
The "nubus-macfb" currently shows up as uncategorized device in
the output of "-device help". Put it into the display category
to fix this ugliness.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210531073255.46286-1-thuth@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:21:56 +02:00
Pavel Dovgalyuk
dd69218949 target/nios2: fix page-fit instruction count
This patch fixes calculation of number of the instructions
that fit the current page. It prevents creation of the translation
blocks that cross the page boundaries. It is required for deterministic
exception generation in icount mode.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <162072241046.823357.10485774346114851009.stgit@pasha-ThinkPad-X280>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:17:10 +02:00
John Snow
d7878875ae docs: fix broken reference
Long story short, we need a space here for the reference to work
correctly.

Longer story:

Without the space, kerneldoc generates a line like this:

one of :c:type:`MemoryListener.region_add\(\) <MemoryListener>`,:c:type:`MemoryListener.region_del\(\)

Sphinx does not process the role information correctly, so we get this
(my pseudo-notation) construct:

<text>,:c:type:</text>
<reference target="MemoryListener">MemoryListener.region_del()</reference>

which does not reference the desired entity, and leaves some extra junk
in the rendered output. See
https://qemu-project.gitlab.io/qemu/devel/memory.html#c.MemoryListener
member log_start for an example of the broken output as it looks today.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210511192950.2061326-1-jsnow@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:15:22 +02:00
Philippe Mathieu-Daudé
180d4ef3ad linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[]
Keep bitmask_transtbl in .rodata by marking the arrays const.

Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210517055243.830491-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:13:29 +02:00
Philippe Mathieu-Daudé
585190902a misc: Correct relative include path
Headers should be included from the 'include/' directory,
not from the root directory.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210516205034.694788-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:10:42 +02:00
Dmitry Voronetskiy
d84451d38e i386/kvm: The value passed to strerror should be positive
Signed-off-by: Dmitry Voronetskiy <vda1999@yandex.ru>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20210519113528.12474-1-davoronetskiy@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 21:01:17 +02:00
Philippe Mathieu-Daudé
0d42cd5c1d target/riscv: Do not include 'pmp.h' in user emulation
Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210516205333.696094-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-05 20:58:43 +02:00
Peter Maydell
6f398e533f Host vector support for arm neon.
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Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210604' into staging

Host vector support for arm neon.

# gpg: Signature made Fri 04 Jun 2021 19:56:59 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210604:
  tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
  tcg/arm: Implement TCG_TARGET_HAS_roti_vec
  tcg/arm: Implement TCG_TARGET_HAS_shv_vec
  tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
  tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
  tcg/arm: Implement TCG_TARGET_HAS_sat_vec
  tcg/arm: Implement TCG_TARGET_HAS_mul_vec
  tcg/arm: Implement TCG_TARGET_HAS_shi_vec
  tcg/arm: Implement andc, orc, abs, neg, not vector operations
  tcg/arm: Implement minimal vector operations
  tcg/arm: Implement tcg_out_dup*_vec
  tcg/arm: Implement tcg_out_mov for vector types
  tcg/arm: Implement tcg_out_ld/st for vector types
  tcg/arm: Add host vector framework
  tcg: Change parameters for tcg_target_const_match

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-05 11:25:52 +01:00
Richard Henderson
0006039e29 tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
5047ae648b tcg/arm: Implement TCG_TARGET_HAS_roti_vec
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
31d366390c tcg/arm: Implement TCG_TARGET_HAS_shv_vec
The three vector shift by vector operations are all implemented via
expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
f2b46c7162 tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
dbbeff7764 tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
This is minimum and maximum, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
4fcd301707 tcg/arm: Implement TCG_TARGET_HAS_sat_vec
This is saturating add and subtract, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
752b17693e tcg/arm: Implement TCG_TARGET_HAS_mul_vec
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
d4c4e9c51b tcg/arm: Implement TCG_TARGET_HAS_shi_vec
This consists of the three immediate shifts: shli, shri, sari.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
7df44cf6e9 tcg/arm: Implement andc, orc, abs, neg, not vector operations
These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
d74b86ed4a tcg/arm: Implement minimal vector operations
Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
213e8d8473 tcg/arm: Implement tcg_out_dup*_vec
Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
2df2a8cf77 tcg/arm: Implement tcg_out_mov for vector types
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
6e49fad23f tcg/arm: Implement tcg_out_ld/st for vector types
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
000cf4777a tcg/arm: Add host vector framework
Add registers and function stubs.  The functionality
is disabled via use_neon_instructions defined to 0.

We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Richard Henderson
a4fbbd779a tcg: Change parameters for tcg_target_const_match
Change the return value to bool, because that's what is should
have been from the start.  Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.

Change the value argument to int64_t.  We will need the extra
width for 32-bit hosts wanting to match vector constants.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04 11:50:11 -07:00
Peter Maydell
908a87706e * OpenBSD cleanup (Brad)
* fixes for the i386 accel/cpu refactoring (Claudio)
 * unmap test for emulated SCSI (Kit)
 * fix for iscsi module (myself)
 * fix for -readconfig of objects (myself)
 * fixes for x86 16-bit task switching (myself)
 * fix for x86 MOV from/to CR8 (Richard)
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Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* OpenBSD cleanup (Brad)
* fixes for the i386 accel/cpu refactoring (Claudio)
* unmap test for emulated SCSI (Kit)
* fix for iscsi module (myself)
* fix for -readconfig of objects (myself)
* fixes for x86 16-bit task switching (myself)
* fix for x86 MOV from/to CR8 (Richard)

# gpg: Signature made Fri 04 Jun 2021 12:53:32 BST
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream:
  vl: plug -object back into -readconfig
  vl: plumb keyval-based options into -readconfig
  qemu-config: parse configuration files to a QDict
  i386: run accel_cpu_instance_init as post_init
  i386: reorder call to cpu_exec_realizefn
  tests/qtest/virtio-scsi-test: add unmap large LBA with 4k blocks test
  target/i386: Fix decode of cr8
  target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa
  target/i386: tcg: fix loading of registers from 16-bit TSS
  target/i386: tcg: fix segment register offsets for 16-bit TSS
  oslib-posix: Remove OpenBSD workaround for fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure
  iscsi: link libm into the module
  meson: allow optional dependencies for block modules

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-04 17:27:29 +01:00
Peter Maydell
1cbd2d9149 -----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
 
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 =m1ZO
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging

# gpg: Signature made Fri 04 Jun 2021 08:26:16 BST
# gpg:                using RSA key EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211

* remotes/jasowang/tags/net-pull-request:
  MAINTAINERS: Added eBPF maintainers information.
  docs: Added eBPF documentation.
  virtio-net: Added eBPF RSS to virtio-net.
  ebpf: Added eBPF RSS loader.
  ebpf: Added eBPF RSS program.
  net: Added SetSteeringEBPF method for NetClientState.
  net/tap: Added TUNSETSTEERINGEBPF code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-04 13:38:49 +01:00
Paolo Bonzini
49e987695a vl: plug -object back into -readconfig
Commit bc2f4fcb1d ("qom: move user_creatable_add_opts logic to vl.c
and QAPIfy it", 2021-03-19) switched the creation of objects from
qemu_opts_foreach to a bespoke QTAILQ in preparation for supporting JSON
syntax in -object.

Unfortunately in doing so it lost support for [object] stanzas in
configuration files and also for "-set object.ID.KEY=VAL".  The latter
is hard to re-establish and probably best solved by deprecating -set.
This patch uses the infrastructure introduced by the previous two
patches in order to parse QOM objects correctly from configuration
files.

Cc: Markus Armbruster <armbru@redhat.com>
Cc: qemu-stable@nongnu.org
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210524105752.3318299-4-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:50:04 +02:00
Paolo Bonzini
c0d4aa82f8 vl: plumb keyval-based options into -readconfig
Let -readconfig support parsing command line options into QDict or
QemuOpts.  This will be used to add back support for objects in
-readconfig.

Cc: Markus Armbruster <armbru@redhat.com>
Cc: qemu-stable@nongnu.org
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210524105752.3318299-3-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:50:04 +02:00
Paolo Bonzini
3770141139 qemu-config: parse configuration files to a QDict
Change the parser to put the values into a QDict and pass them
to a callback.  qemu_config_parse's QemuOpts creation is
itself turned into a callback function.

This is useful for -readconfig to support keyval-based options;
getting a QDict from the parser removes a roundtrip from
QDict to QemuOpts and then back to QDict.

Unfortunately there is a disadvantage in that semantic errors will
point to the last line of the group, because the entries of the QDict
do not have a location attached.

Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Markus Armbruster <armbru@redhat.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210524105752.3318299-2-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:50:01 +02:00
Claudio Fontana
4db4385a7a i386: run accel_cpu_instance_init as post_init
This fixes host and max cpu initialization, by running the accel cpu
initialization only after all instance init functions are called for all
X86 cpu subclasses.

The bug this is fixing is related to the "max" and "host" i386 cpu
subclasses, which set cpu->max_features, which is then used at cpu
realization time.

In order to properly split the accel-specific max features code that
needs to be executed at cpu instance initialization time,

we cannot call the accel cpu initialization at the end of the x86 base
class initialization, or we will have no way to specialize
"max features" cpu behavior, overriding the "max" cpu class defaults,
and checking for the "max features" flag itself.

This patch moves the accel-specific cpu instance initialization to after
all x86 cpu instance code has been executed, including subclasses,

so that proper initialization of cpu "host" and "max" can be restored.

Fixes: f5cc5a5c ("i386: split cpu accelerators from cpu.c,"...)
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210603123001.17843-3-cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:47:08 +02:00
Claudio Fontana
662175b91f i386: reorder call to cpu_exec_realizefn
i386 realizefn code is sensitive to ordering, and recent commits
aimed at refactoring it, splitting accelerator-specific code,
broke assumptions which need to be fixed.

We need to:

* process hyper-v enlightements first, as they assume features
  not to be expanded

* only then, expand features

* after expanding features, attempt to check them and modify them in the
  accel-specific realizefn code called by cpu_exec_realizefn().

* after the framework has been called via cpu_exec_realizefn,
  the code can check for what has or hasn't been set by accel-specific
  code, or extend its results, ie:

  - check and evenually set code_urev default
  - modify cpu->mwait after potentially being set from host CPUID.
  - finally check for phys_bits assuming all user and accel-specific
    adjustments have already been taken into account.

Fixes: f5cc5a5c ("i386: split cpu accelerators from cpu.c"...)
Fixes: 30565f10 ("cpu: call AccelCPUClass::cpu_realizefn in"...)
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210603123001.17843-2-cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:47:08 +02:00
Kit Westneat
6b731a96aa tests/qtest/virtio-scsi-test: add unmap large LBA with 4k blocks test
Add test for issue #345

Signed-off-by: Kit Westneat <kit.westneat@gmail.com>
Message-Id: <20210603142022.676395-1-kit.westneat@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:47:08 +02:00
Richard Henderson
e18a6ec8c4 target/i386: Fix decode of cr8
A recent cleanup did not recognize that there are two ways
to encode cr8: one via the LOCK and the other via REX.

Fixes: 7eff2e7c
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/380
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210602035511.96834-1-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:47:08 +02:00
Paolo Bonzini
1b627f389f target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa
The format of the task state segment is governed by bit 3 in the
descriptor type field.  On a task switch, the format for saving
is given by the current value of TR's type field, while the
format for loading is given by the new descriptor.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:47:08 +02:00
Paolo Bonzini
a5505f6b5b target/i386: tcg: fix loading of registers from 16-bit TSS
According to the manual, the high 16-bit of the registers are preserved
when switching to a 16-bit task.  Implement this in switch_tss_ra.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-04 13:47:08 +02:00