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tcg/arm: Implement TCG_TARGET_HAS_roti_vec

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Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-09-05 13:26:48 -07:00
parent 31d366390c
commit 5047ae648b
3 changed files with 17 additions and 0 deletions
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1
tcg/arm/tcg-target-con-set.h
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@ -30,6 +30,7 @@ C_O1_I2(r, r, rIK)
C_O1_I2(r, r, rIN)
C_O1_I2(r, r, ri)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, 0, w)
C_O1_I2(w, w, w)
C_O1_I2(w, w, wO)
C_O1_I2(w, w, wV)

15
tcg/arm/tcg-target.c.inc
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@ -212,6 +212,7 @@ typedef enum {
INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */
INSN_VSARI = 0xf2800010, /* VSHR.S */
INSN_VSHRI = 0xf3800010, /* VSHR.U */
INSN_VSLI = 0xf3800510,
INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */
INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */
@ -2423,6 +2424,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_arm_sshl_vec:
case INDEX_op_arm_ushl_vec:
return C_O1_I2(w, w, w);
case INDEX_op_arm_sli_vec:
return C_O1_I2(w, 0, w);
case INDEX_op_or_vec:
case INDEX_op_andc_vec:
return C_O1_I2(w, w, wO);
@ -2835,6 +2838,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sari_vec:
tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
return;
case INDEX_op_arm_sli_vec:
tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
return;
case INDEX_op_andc_vec:
if (!const_args[2]) {
@ -2963,6 +2969,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
case INDEX_op_rotli_vec:
return -1;
default:
return 0;
@ -3010,6 +3017,14 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
tcg_temp_free_vec(t1);
break;
case INDEX_op_rotli_vec:
t1 = tcg_temp_new_vec(type);
tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
vec_gen_4(INDEX_op_arm_sli_vec, type, vece,
tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
tcg_temp_free_vec(t1);
break;
default:
g_assert_not_reached();
}

1
tcg/arm/tcg-target.opc.h
View File

@ -11,5 +11,6 @@
* consider these to be UNSPEC with names.
*/
DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)