tcg/arm: Implement TCG_TARGET_HAS_rotv_vec

Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-09-05 14:20:57 -07:00
parent 5047ae648b
commit 0006039e29

View File

@ -2970,6 +2970,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
case INDEX_op_rotli_vec:
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
return -1;
default:
return 0;
@ -2980,7 +2982,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
va_list va;
TCGv_vec v0, v1, v2, t1;
TCGv_vec v0, v1, v2, t1, t2, c1;
TCGArg a2;
va_start(va, a0);
@ -3025,6 +3027,37 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
tcg_temp_free_vec(t1);
break;
case INDEX_op_rotlv_vec:
v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
tcg_gen_sub_vec(vece, t1, v2, c1);
/* Right shifts are negative left shifts for NEON. */
vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
tcgv_vec_arg(v1), tcgv_vec_arg(t1));
vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
tcgv_vec_arg(v1), tcgv_vec_arg(v2));
tcg_gen_or_vec(vece, v0, v0, t1);
tcg_temp_free_vec(t1);
break;
case INDEX_op_rotrv_vec:
v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
t2 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
tcg_gen_neg_vec(vece, t1, v2);
tcg_gen_sub_vec(vece, t2, c1, v2);
/* Right shifts are negative left shifts for NEON. */
vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
tcgv_vec_arg(v1), tcgv_vec_arg(t1));
vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
tcgv_vec_arg(v1), tcgv_vec_arg(t2));
tcg_gen_or_vec(vece, v0, t1, t2);
tcg_temp_free_vec(t1);
tcg_temp_free_vec(t2);
break;
default:
g_assert_not_reached();
}