Paolo Bonzini
10eb0cc03c
move cpu_pc_from_tb to target-*/exec.h
...
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Nathan Froyd
bbfa8f72e9
target-mips: add microMIPS exception handler support
...
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers. The ISA mode is selectable via a user-writable CP0.Config3
flag.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:51 +02:00
Paul Brook
3c7b48b74c
Target specific usermode cleanup
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Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:44:24 +00:00
Aurelien Jarno
c36bbb28ad
target-mips: don't call cpu_loop_exit() from helper.c
...
In helper.c AREG0 may not correspond do env, so it's not possible to
call cpu_loop_exit() here. Call it from op_helper.c instead.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:23:33 +01:00
Nathan Froyd
79ef2c4cdb
target-mips: add new HFLAGs for JALX and 16/32-bit delay slots
...
We create separate masks for the "basic" branch hflags and the
"extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or
of those two. This is done to avoid churning the codebase in lots of
different places.
We also make the execution mode an hflag under MIPS_HFLAG_TMASK
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Aurelien Jarno
25b91e32e0
target-mips: add a function to do virtual -> physical translations
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:10:04 +01:00
Aurelien Jarno
60c9af07aa
target-mips: fix physical address type in MMU functions
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:37:04 +01:00
Aurelien Jarno
2a6e32dd46
target-mips: make CP0_LLAddr register CPU dependent
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Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22 14:12:19 +01:00
Aurelien Jarno
5499b6ffac
target-mips: rename CP0_LLAddr into lladdr
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The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:12:13 +01:00
Blue Swirl
51cc2e783a
mips: fix cpu_reset memory leak
...
Remove cpu_mips_register()
- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()
- move the other parts in cpu_mips_init()
Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 02:25:52 +01:00
Anthony Liguori
c227f0995e
Revert "Get rid of _t suffix"
...
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72
.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72
Get rid of _t suffix
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Some not so obvious bits, slirp and Xen were left alone for the time
being.
Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Nathan Froyd
0b5c1ce846
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
...
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations. This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently. Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.
Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality. I have removed
such blocks for the appropriate targets in this patch.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Juan Quintela
e2542fe2bc
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
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Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela
dfe5fff3ea
change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
...
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:16 -05:00
Paul Brook
590bc601d8
MIPS atomic instructions
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Implement MIPS ll/sc instructions using atomic compare+exchange.
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09 17:45:17 +01:00
Paul Brook
ff867ddcbd
MIPS usermode TLS register
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Implement cpu_set_tls for MIPS.
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09 15:07:57 +01:00
aurel32
1ba74fb8f1
target-mips: optimize gen_compute_branch()
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6936 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:52 +00:00
aurel32
c01fccd2de
target-mips: rename helpers from do_ to helper_
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08 00:06:01 +00:00
pbrook
c276471991
The _exit syscall is used for both thread termination in NPTL applications,
...
and process termination in legacy applications. Try to guess which we want
based on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:24:59 +00:00
ths
f9480ffc14
Fix remaining compiler warnings for mips targets.
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Signed-off-by: Stefan Weil <weil@mail.berlios.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6111 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-20 19:42:14 +00:00
aliguori
6b9175478e
Refactor translation block CPU state handling (Jan Kiszka)
...
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:46:41 +00:00
aliguori
622ed3605b
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
...
as macros should be avoided when possible.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18 19:36:03 +00:00
aurel32
2623c1ecfc
target-mips: optimize gen_op_addr_add() (2/2)
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Instead of dynamically generating different code depending on the UX
flag, add a new flag in ctx->flags to generate different code.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5677 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:39:33 +00:00
blueswir1
e18231a3ff
Show size for unassigned accesses (Robert Reif)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-06 18:46:28 +00:00
ths
f01be15458
Move the active FPU registers into env again, and use more TCG registers
...
to access them.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18 11:57:27 +00:00
ths
0eaef5aa01
Less hardcoding of TARGET_USER_ONLY.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23 16:14:22 +00:00
ths
b6d96beda3
Use temporary registers for the MIPS FPU emulation.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-09 11:05:10 +00:00
pbrook
9656f324d2
Move interrupt_request and user_mode_only to common cpu state.
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Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01 20:01:19 +00:00
pbrook
b3c7724cbc
Move CPU save/load registration to common code.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-30 16:31:04 +00:00
pbrook
2e70f6efa8
Add instruction counter.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29 01:03:05 +00:00
ths
b5dc7732e1
More efficient target register / TC accesses.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4794 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-27 10:02:35 +00:00
ths
1a3fd9c3da
Remove remaining uses of T0 in the MIPS target.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 21:58:35 +00:00
ths
e1bf387ec8
T1 is now dead.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4787 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-24 20:13:20 +00:00
ths
764dfc3fa0
Move FP TNs to cpu env.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4728 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-11 10:39:48 +00:00
pbrook
f8ed7070ea
Fix typo.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:54:15 +00:00
pbrook
6e68e076e7
Move clone() register setup to target specific code. Handle fork-like clone.
...
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30 17:22:15 +00:00
bellard
9133e39b84
Push common interrupt variables to cpu-defs.h (Glauber Costa)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29 10:08:06 +00:00
bellard
ce5232c5c2
moved halted field to CPU_COMMON
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28 17:14:10 +00:00
ths
893f986502
Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4604 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28 13:37:19 +00:00
ths
958fb4a92c
Use TCG for MIPS GPR moves.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4356 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-06 10:57:59 +00:00
ths
3945462805
Simplify mips branch handling. Retire T2 from use. Use TCG for branches.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4320 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04 08:16:10 +00:00
ths
d0dc7dc327
Make MIPS MT implementation more cache friendly.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3981 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-12 21:01:26 +00:00
ths
b8aa4598e2
MIPS COP1X (and related) instructions, by Richard Sandiford.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3877 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-30 15:36:58 +00:00
ths
14e51cc7a4
De-cruft exception definitions, and implement nicer debug output.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3861 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-26 19:34:03 +00:00
ths
6d35524c40
Improved PABITS handling, and config register fixes.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3855 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-25 03:13:56 +00:00
bellard
aaed909a49
added cpu_model parameter to cpu_init()
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 15:15:54 +00:00
ths
7df526e317
Move kernel loader parameters from the cpu state to being board specific.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3557 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-09 17:52:11 +00:00
ths
623a930ec3
Implement missing MIPS supervisor mode bits.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28 19:45:05 +00:00
ths
647de6ca24
Handle IBE on MIPS properly.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3416 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-20 19:45:44 +00:00
j_mayer
6ebbf39000
Replace is_user variable with mmu_idx in softmmu core,
...
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
and using the same definition in code translation code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 07:07:08 +00:00
j_mayer
c732abe222
Unify '-cpu ?' option.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-12 06:47:46 +00:00
ths
198a74de4c
Move get_sp_from_cpustate from cpu.h to target_signal.h.
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Enable sigaltstack processing for more architectures.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 16:44:32 +00:00
ths
a04e134ad1
linux-user sigaltstack() syscall, by Thayne Harbaugh.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-27 13:57:58 +00:00
ths
387a8fe505
Optimise instructions accessing CP0, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3235 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-25 14:49:47 +00:00
ths
e189e74868
Per-CPU instruction decoding implementation, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-24 12:48:00 +00:00
ths
ead9360e2f
Partial support for 34K multithreading, not functional yet.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-06 00:18:15 +00:00
ths
e034e2c39a
Handle MIPS64 SEGBITS value correctly.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3011 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-23 18:04:12 +00:00
ths
9467d44c4d
Move target-specific defines to the target directories.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-03 21:02:38 +00:00
ths
33ac7f1630
Don't kill the registered irqs on reset.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2903 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-31 16:18:58 +00:00
ths
51b2772f28
Fix CPU (re-)selection on reset.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2900 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-30 20:46:02 +00:00
ths
78749ba859
Fix usermode check, thanks Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2897 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-29 18:55:34 +00:00
ths
5e755519ac
Don't check the FPU state for each FPU instruction, use hflags to
...
handle this per-tb.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2896 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-29 16:52:57 +00:00
ths
6e473128b6
Handle PX/UX status flags correctly, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2892 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-28 20:36:48 +00:00
ths
fd88b6abab
The 24k wants more watch and srsmap registers.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2849 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-23 08:24:25 +00:00
ths
fd4a04ebb2
- Move FPU exception handling into helper functions, since they are big.
...
- Fix FP-conditional branches.
- Check FPU register mode at runtime, not translation time, as the F64
status bit can change.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2828 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-18 11:55:54 +00:00
ths
388bb21af6
MIPS linux-user update.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2810 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13 13:58:00 +00:00
ths
29929e3490
MIPS TLB style selection at runtime, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-13 13:49:44 +00:00
ths
5a5012ecbd
MIPS 64-bit FPU support, plus some collateral bugfixes in the
...
conditional branch handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-07 13:55:33 +00:00
ths
fcb4a419f5
Choose number of TLBs at runtime, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-17 15:26:47 +00:00
pbrook
d537cf6c86
Unify IRQ handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-07 18:14:41 +00:00
ths
f7cfb2a176
64bit MIPS FPUs have 32 registers.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-05 23:14:23 +00:00
ths
36bb244bd3
Fix typo, suggested by Ben Taylor.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2548 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30 18:42:21 +00:00
ths
24c7b0e330
Sanitize mips exception handling.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2546 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-30 16:44:54 +00:00
ths
e397ee3382
Fix enough FPU/R2 support to get 24Kf going.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2528 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-23 00:43:28 +00:00
ths
33d68b5f00
MIPS -cpu selection support, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2491 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-18 00:30:29 +00:00
ths
6f5b89a07c
MIPS Userland TLS register emulation, by Daniel Jacobowitz.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2465 c046a42c-6fe2-441c-8c8c-71466251a162
2007-03-02 20:48:00 +00:00
ths
36d2395873
MIPS FPU dynamic activation, part 1, by Herve Poussineau.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-28 22:37:42 +00:00
ths
3594c77487
Replace TLSZ with TARGET_FMT_lx.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2444 c046a42c-6fe2-441c-8c8c-71466251a162
2007-02-20 23:37:21 +00:00
ths
b29a0341d7
EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-24 18:01:23 +00:00
ths
4de9b249d3
Reworking MIPS interrupt handling, by Aurelien Jarno.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-24 01:47:51 +00:00
ths
9c2149c8e0
Implementing dmfc/dmtc.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2348 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-23 22:45:22 +00:00
ths
3b1c8be4f4
Fix PageMask handling, second part.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2345 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-22 20:50:42 +00:00
ths
9042c0e20d
Check ELF binaries for machine type and endianness.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2274 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-23 14:18:40 +00:00
ths
5dc4b74480
Scrap SIGN_EXTEND32.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2251 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21 13:48:28 +00:00
ths
c570fd169c
Preliminiary MIPS64 support, disabled by default due to performance impact.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-21 01:19:56 +00:00
ths
7a387fffce
Add MIPS32R2 instructions, and generally straighten out the instruction
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decoding. This is also the first percent towards MIPS64 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06 20:17:30 +00:00
ths
6ae817752b
Halt/reboot support for Linux, by Daniel Jacobowitz. This is a band-aid
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until we emulate real MIPS hardware with real firmware.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2221 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06 17:48:52 +00:00
ths
814b9a4749
MIPS TLB performance improvements, by Daniel Jacobowitz.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2220 c046a42c-6fe2-441c-8c8c-71466251a162
2006-12-06 17:42:40 +00:00
bellard
fdbb46910a
Solaris/SPARC host port (Ben Taylor)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1979 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-14 17:32:25 +00:00
bellard
43057ab127
use constants for TLB handling (Thiemo Seufer)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1978 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-14 17:15:19 +00:00
bellard
c5d6edc3fc
mips config fixes (initial patch by Stefan Weil)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1977 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-14 16:49:24 +00:00
bellard
6ea83fedc8
MIPS FPU support (Marius Goeger)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1964 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-14 12:56:19 +00:00
pbrook
56b194039e
Rename MIPS_HFLAG(S)_TMASK (Thiemo Seufer).
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1775 c046a42c-6fe2-441c-8c8c-71466251a162
2006-03-11 16:23:39 +00:00
pbrook
98c1b82b6c
e bitfields in mips TLB structures (Thiemo Seufer).
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1774 c046a42c-6fe2-441c-8c8c-71466251a162
2006-03-11 16:20:36 +00:00
bellard
4ad40f366f
MIPS fixes (Daniel Jacobowitz)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1690 c046a42c-6fe2-441c-8c8c-71466251a162
2005-12-05 19:59:36 +00:00
bellard
a316d3353c
added CPU_COMMON and CPUState.tb_jmp_cache[]
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1630 c046a42c-6fe2-441c-8c8c-71466251a162
2005-11-20 10:32:34 +00:00
bellard
e37e863f5e
correct split between helper.c and op_helper.c - cosmetics
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1505 c046a42c-6fe2-441c-8c8c-71466251a162
2005-07-04 22:17:33 +00:00
bellard
6af0bf9c7c
MIPS target (Jocelyn Mayer)
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1464 c046a42c-6fe2-441c-8c8c-71466251a162
2005-07-02 14:58:51 +00:00