2007-11-17 20:14:51 +03:00
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#ifndef QEMU_PCI_H
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#define QEMU_PCI_H
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2012-12-17 21:19:49 +04:00
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#include "exec/memory.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/dma.h"
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2009-05-15 01:35:07 +04:00
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2007-11-17 20:14:51 +03:00
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/* PCI includes legacy ISA access. */
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2013-02-05 20:06:20 +04:00
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#include "hw/isa/isa.h"
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2007-11-17 20:14:51 +03:00
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2017-07-07 12:45:26 +03:00
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extern bool pci_available;
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2007-11-17 20:14:51 +03:00
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/* PCI bus */
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2009-02-11 18:19:46 +03:00
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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2016-09-20 18:42:31 +03:00
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#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
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2009-02-11 18:19:46 +03:00
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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2016-05-17 14:26:10 +03:00
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#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
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2022-06-13 23:26:33 +03:00
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#define PCI_BDF_TO_DEVFN(x) ((x) & 0xff)
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2016-09-20 18:42:31 +03:00
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#define PCI_BUS_MAX 256
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#define PCI_DEVFN_MAX 256
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2011-01-27 09:56:35 +03:00
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#define PCI_SLOT_MAX 32
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2010-06-23 11:15:26 +04:00
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#define PCI_FUNC_MAX 8
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2009-02-11 18:19:46 +03:00
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2009-03-13 18:02:23 +03:00
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/* Class, Vendor and Device IDs from Linux's pci_ids.h */
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2012-12-13 01:05:42 +04:00
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#include "hw/pci/pci_ids.h"
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2009-02-01 22:26:20 +03:00
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2009-03-13 18:02:23 +03:00
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/* QEMU-specific Vendor and Device ID definitions */
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2009-02-11 18:21:54 +03:00
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2009-03-13 18:02:23 +03:00
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/* IBM (0x1014) */
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#define PCI_DEVICE_ID_IBM_440GX 0x027f
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2009-02-01 15:01:04 +03:00
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#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
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2009-01-26 18:37:35 +03:00
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2009-03-13 18:02:23 +03:00
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/* Hitachi (0x1054) */
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2009-01-26 18:37:35 +03:00
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#define PCI_VENDOR_ID_HITACHI 0x1054
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2009-03-13 18:02:23 +03:00
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#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
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2009-01-26 18:37:35 +03:00
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2009-03-13 18:02:23 +03:00
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/* Apple (0x106b) */
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2009-02-01 15:01:04 +03:00
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#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
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#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
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#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
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#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
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2009-03-13 18:02:23 +03:00
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#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
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2009-01-26 18:37:35 +03:00
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2009-03-13 18:02:23 +03:00
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/* Realtek (0x10ec) */
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#define PCI_DEVICE_ID_REALTEK_8029 0x8029
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2009-01-26 18:37:35 +03:00
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2009-03-13 18:02:23 +03:00
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/* Xilinx (0x10ee) */
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#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
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2009-01-26 18:37:35 +03:00
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2009-03-13 18:02:23 +03:00
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/* Marvell (0x11ab) */
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#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
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2009-01-26 18:37:35 +03:00
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2009-03-13 18:02:23 +03:00
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/* QEMU/Bochs VGA (0x1234) */
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2009-02-01 15:01:04 +03:00
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#define PCI_VENDOR_ID_QEMU 0x1234
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#define PCI_DEVICE_ID_QEMU_VGA 0x1111
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2017-12-06 22:36:21 +03:00
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#define PCI_DEVICE_ID_QEMU_IPMI 0x1112
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2009-02-01 15:01:04 +03:00
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2009-03-13 18:02:23 +03:00
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/* VMWare (0x15ad) */
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2009-01-26 18:37:35 +03:00
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#define PCI_VENDOR_ID_VMWARE 0x15ad
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#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
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#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
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#define PCI_DEVICE_ID_VMWARE_NET 0x0720
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#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
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2013-04-19 11:05:46 +04:00
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#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
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2009-01-26 18:37:35 +03:00
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#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
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2013-03-09 13:21:06 +04:00
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#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
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2009-01-26 18:37:35 +03:00
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2009-03-28 20:29:07 +03:00
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/* Intel (0x8086) */
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2009-03-13 18:02:23 +03:00
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#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
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2009-09-02 00:16:10 +04:00
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#define PCI_DEVICE_ID_INTEL_82557 0x1229
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2010-12-14 03:34:39 +03:00
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#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
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2009-03-02 19:42:23 +03:00
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2009-01-26 18:37:35 +03:00
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/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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2008-12-12 00:15:42 +03:00
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#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBDEVICE_ID_QEMU 0x1100
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2022-10-04 14:21:00 +03:00
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/* legacy virtio-pci devices */
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2008-12-12 00:15:42 +03:00
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#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
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#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
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#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
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2009-01-26 18:22:46 +03:00
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#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
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2011-02-11 11:40:59 +03:00
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#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
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2012-06-20 10:59:32 +04:00
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#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
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2012-12-13 13:19:36 +04:00
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#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
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2016-08-16 15:27:22 +03:00
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#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
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2008-12-12 00:15:42 +03:00
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2022-10-04 14:21:00 +03:00
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/*
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* modern virtio-pci devices get their id assigned automatically,
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* there is no need to add #defines here. It gets calculated as
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*
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* PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE +
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* virtio_bus_get_vdev_id(bus)
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*/
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#define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040
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2008-12-12 00:15:42 +03:00
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2012-12-13 13:19:38 +04:00
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#define PCI_VENDOR_ID_REDHAT 0x1b36
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#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
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#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
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#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
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#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
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2013-03-31 16:31:14 +04:00
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#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
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2015-03-14 07:09:28 +03:00
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#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
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2014-12-30 08:14:02 +03:00
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#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
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2015-02-13 08:46:07 +03:00
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#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
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2015-06-02 14:23:06 +03:00
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#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
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2015-06-18 13:17:29 +03:00
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#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
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2015-11-26 19:00:27 +03:00
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#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
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2017-01-23 22:20:20 +03:00
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#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
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2017-02-06 14:55:37 +03:00
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#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
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2017-08-18 02:36:47 +03:00
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#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
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2018-04-24 09:38:57 +03:00
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#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
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2020-01-13 21:12:50 +03:00
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#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
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2021-01-27 17:59:28 +03:00
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#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
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2022-01-28 23:38:02 +03:00
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#define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
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2023-09-06 10:43:48 +03:00
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#define PCI_DEVICE_ID_REDHAT_UFS 0x0013
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2012-12-13 13:19:38 +04:00
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#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
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2009-10-30 15:21:10 +03:00
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#define FMT_PCIBUS PRIx64
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2009-10-30 15:21:08 +03:00
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2016-03-09 15:44:19 +03:00
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typedef uint64_t pcibus_t;
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struct PCIHostDeviceAddress {
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unsigned int domain;
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unsigned int bus;
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unsigned int slot;
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unsigned int function;
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};
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2007-11-17 20:14:51 +03:00
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typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
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uint32_t address, uint32_t data, int len);
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typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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uint32_t address, int len);
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typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
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2009-10-30 15:21:08 +03:00
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pcibus_t addr, pcibus_t size, int type);
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2012-07-04 08:39:27 +04:00
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typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
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2007-11-17 20:14:51 +03:00
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2022-06-13 23:26:33 +03:00
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typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg);
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typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector);
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typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector);
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2007-11-17 20:14:51 +03:00
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typedef struct PCIIORegion {
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2009-10-30 15:21:08 +03:00
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pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
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#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
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pcibus_t size;
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2007-11-17 20:14:51 +03:00
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uint8_t type;
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2011-07-26 15:26:20 +04:00
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MemoryRegion *memory;
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2011-08-08 17:09:05 +04:00
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MemoryRegion *address_space;
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2007-11-17 20:14:51 +03:00
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} PCIIORegion;
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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2013-03-03 21:21:26 +04:00
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enum {
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QEMU_PCI_VGA_MEM,
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QEMU_PCI_VGA_IO_LO,
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QEMU_PCI_VGA_IO_HI,
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QEMU_PCI_VGA_NUM_REGIONS,
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};
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#define QEMU_PCI_VGA_MEM_BASE 0xa0000
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#define QEMU_PCI_VGA_MEM_SIZE 0x20000
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#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
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#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
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#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
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#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
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2012-12-13 01:05:42 +04:00
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#include "hw/pci/pci_regs.h"
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2009-12-15 14:26:01 +03:00
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/* PCI HEADER_TYPE */
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2009-05-03 23:03:00 +04:00
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#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
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2008-12-19 01:43:33 +03:00
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2009-06-21 20:45:18 +04:00
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/* Size of the standard PCI config header */
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#define PCI_CONFIG_HEADER_SIZE 0x40
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100
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2015-03-10 04:52:23 +03:00
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/* Size of the standard PCIe config space: 4KB */
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2009-10-30 15:21:18 +03:00
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#define PCIE_CONFIG_SPACE_SIZE 0x1000
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2009-06-21 20:45:18 +04:00
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2009-10-30 15:20:56 +03:00
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#define PCI_NUM_PINS 4 /* A-D */
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2009-06-21 20:49:54 +04:00
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/* Bits in cap_present field. */
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enum {
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2010-10-19 13:06:32 +04:00
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QEMU_PCI_CAP_MSI = 0x1,
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QEMU_PCI_CAP_MSIX = 0x2,
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QEMU_PCI_CAP_EXPRESS = 0x4,
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2010-06-23 11:15:30 +04:00
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/* multifunction capable device */
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2010-10-19 13:06:32 +04:00
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#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
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2010-06-23 11:15:30 +04:00
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QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
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2010-11-26 15:01:41 +03:00
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2019-12-09 15:52:47 +03:00
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/* command register SERR bit enabled - unused since QEMU v5.0 */
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2010-11-26 15:01:41 +03:00
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#define QEMU_PCI_CAP_SERR_BITNR 4
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QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
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2012-02-12 16:12:21 +04:00
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/* Standard hot plug controller. */
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#define QEMU_PCI_SHPC_BITNR 5
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QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
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2012-02-15 21:17:59 +04:00
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#define QEMU_PCI_SLOTID_BITNR 6
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QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
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2014-06-23 18:32:48 +04:00
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/* PCI Express capability - Power Controller Present */
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#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
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QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
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2016-07-19 23:16:19 +03:00
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/* Link active status in endpoint capability is always set */
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#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
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QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
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2017-02-20 23:43:10 +03:00
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#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
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QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
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2022-04-29 17:40:26 +03:00
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#define QEMU_PCIE_CXL_BITNR 10
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QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
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2023-05-03 03:27:02 +03:00
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#define QEMU_PCIE_ERR_UNC_MASK_BITNR 11
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QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR),
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2023-07-10 18:38:36 +03:00
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#define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12
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QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR),
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2009-06-21 20:49:54 +04:00
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};
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2012-07-19 18:11:47 +04:00
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typedef struct PCIINTxRoute {
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enum {
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PCI_INTX_ENABLED,
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PCI_INTX_INVERTED,
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PCI_INTX_DISABLED,
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} mode;
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int irq;
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} PCIINTxRoute;
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2012-07-02 16:38:47 +04:00
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typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
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2012-05-17 17:32:31 +04:00
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typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
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MSIMessage msg);
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typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
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2012-12-12 18:10:02 +04:00
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typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
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unsigned int vector_start,
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unsigned int vector_end);
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2012-05-17 17:32:31 +04:00
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2011-08-08 17:09:31 +04:00
|
|
|
void pci_register_bar(PCIDevice *pci_dev, int region_num,
|
|
|
|
uint8_t attr, MemoryRegion *memory);
|
2013-03-03 21:21:26 +04:00
|
|
|
void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
|
|
|
|
MemoryRegion *io_lo, MemoryRegion *io_hi);
|
|
|
|
void pci_unregister_vga(PCIDevice *pci_dev);
|
2011-08-08 17:08:55 +04:00
|
|
|
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
|
2007-11-17 20:14:51 +03:00
|
|
|
|
2010-09-06 11:46:16 +04:00
|
|
|
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
2017-06-27 09:16:50 +03:00
|
|
|
uint8_t offset, uint8_t size,
|
|
|
|
Error **errp);
|
2009-06-21 20:45:40 +04:00
|
|
|
|
|
|
|
void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
|
|
|
|
|
|
|
|
uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
|
|
|
|
|
|
|
|
|
2007-11-17 20:14:51 +03:00
|
|
|
uint32_t pci_default_read_config(PCIDevice *d,
|
|
|
|
uint32_t address, int len);
|
|
|
|
void pci_default_write_config(PCIDevice *d,
|
|
|
|
uint32_t address, uint32_t val, int len);
|
|
|
|
void pci_device_save(PCIDevice *s, QEMUFile *f);
|
|
|
|
int pci_device_load(PCIDevice *s, QEMUFile *f);
|
2011-08-15 18:17:36 +04:00
|
|
|
MemoryRegion *pci_address_space(PCIDevice *dev);
|
2011-08-11 02:28:10 +04:00
|
|
|
MemoryRegion *pci_address_space_io(PCIDevice *dev);
|
2007-11-17 20:14:51 +03:00
|
|
|
|
2015-05-07 08:33:54 +03:00
|
|
|
/*
|
|
|
|
* Should not normally be used by devices. For use by sPAPR target
|
|
|
|
* where QEMU emulates firmware.
|
|
|
|
*/
|
|
|
|
int pci_bar(PCIDevice *d, int reg);
|
|
|
|
|
2009-08-28 17:28:17 +04:00
|
|
|
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
|
2007-11-17 20:14:51 +03:00
|
|
|
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
|
2012-07-19 18:11:47 +04:00
|
|
|
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
|
2010-11-12 10:21:35 +03:00
|
|
|
|
2013-03-15 02:01:05 +04:00
|
|
|
#define TYPE_PCI_BUS "PCI"
|
2020-09-16 21:25:18 +03:00
|
|
|
OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
|
2013-03-15 02:01:05 +04:00
|
|
|
#define TYPE_PCIE_BUS "PCIE"
|
2022-04-29 17:40:39 +03:00
|
|
|
#define TYPE_CXL_BUS "CXL"
|
2013-03-15 02:01:05 +04:00
|
|
|
|
2021-10-28 07:31:25 +03:00
|
|
|
typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
|
|
|
|
typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
|
|
|
|
typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
|
|
|
|
|
2023-01-12 17:03:02 +03:00
|
|
|
bool pci_bus_is_express(const PCIBus *bus);
|
2019-04-01 20:55:02 +03:00
|
|
|
|
2021-09-23 15:11:50 +03:00
|
|
|
void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
|
|
|
|
const char *name,
|
2023-10-09 10:33:29 +03:00
|
|
|
MemoryRegion *mem, MemoryRegion *io,
|
2021-09-23 15:11:50 +03:00
|
|
|
uint8_t devfn_min, const char *typename);
|
2017-11-29 11:46:22 +03:00
|
|
|
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
|
2023-10-09 10:33:29 +03:00
|
|
|
MemoryRegion *mem, MemoryRegion *io,
|
2013-03-15 02:01:11 +04:00
|
|
|
uint8_t devfn_min, const char *typename);
|
2018-12-21 03:35:30 +03:00
|
|
|
void pci_root_bus_cleanup(PCIBus *bus);
|
2023-01-09 20:23:17 +03:00
|
|
|
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
|
2009-09-17 00:25:31 +04:00
|
|
|
void *irq_opaque, int nirq);
|
2023-01-09 20:23:17 +03:00
|
|
|
void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
|
2018-12-21 03:35:30 +03:00
|
|
|
void pci_bus_irqs_cleanup(PCIBus *bus);
|
2011-04-01 15:43:21 +04:00
|
|
|
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
|
2023-03-15 17:26:19 +03:00
|
|
|
uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus);
|
|
|
|
void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask);
|
|
|
|
void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask);
|
2012-10-20 00:43:28 +04:00
|
|
|
/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
|
2019-04-05 19:30:48 +03:00
|
|
|
static inline int pci_swizzle(int slot, int pin)
|
|
|
|
{
|
|
|
|
return (slot + pin) % PCI_NUM_PINS;
|
|
|
|
}
|
2012-10-20 00:43:28 +04:00
|
|
|
int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
|
2017-11-29 11:46:22 +03:00
|
|
|
PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
|
|
|
|
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
|
|
|
void *irq_opaque,
|
2023-10-09 10:33:29 +03:00
|
|
|
MemoryRegion *mem, MemoryRegion *io,
|
2017-11-29 11:46:22 +03:00
|
|
|
uint8_t devfn_min, int nirq,
|
|
|
|
const char *typename);
|
2018-12-21 03:35:30 +03:00
|
|
|
void pci_unregister_root_bus(PCIBus *bus);
|
2012-07-19 18:11:47 +04:00
|
|
|
void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
|
|
|
|
PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
|
2012-10-02 23:21:54 +04:00
|
|
|
bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
|
2012-07-02 16:38:47 +04:00
|
|
|
void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
|
|
|
|
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
|
|
|
|
PCIINTxRoutingNotifier notifier);
|
2010-12-22 09:14:35 +03:00
|
|
|
void pci_device_reset(PCIDevice *dev);
|
2007-11-17 20:14:51 +03:00
|
|
|
|
2023-10-20 03:05:31 +03:00
|
|
|
void pci_init_nic_devices(PCIBus *bus, const char *default_model);
|
|
|
|
bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model,
|
|
|
|
const char *alias, const char *devaddr);
|
2012-09-08 13:49:24 +04:00
|
|
|
PCIDevice *pci_vga_init(PCIBus *bus);
|
|
|
|
|
2017-11-29 11:46:27 +03:00
|
|
|
static inline PCIBus *pci_get_bus(const PCIDevice *dev)
|
|
|
|
{
|
|
|
|
return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
|
|
|
|
}
|
2007-11-17 20:14:51 +03:00
|
|
|
int pci_bus_num(PCIBus *s);
|
2021-07-08 15:55:15 +03:00
|
|
|
void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
|
2017-11-29 11:46:26 +03:00
|
|
|
static inline int pci_dev_bus_num(const PCIDevice *dev)
|
|
|
|
{
|
2017-11-29 11:46:27 +03:00
|
|
|
return pci_bus_num(pci_get_bus(dev));
|
2017-11-29 11:46:26 +03:00
|
|
|
}
|
|
|
|
|
2015-06-02 14:23:09 +03:00
|
|
|
int pci_bus_numa_node(PCIBus *bus);
|
2012-06-21 19:35:28 +04:00
|
|
|
void pci_for_each_device(PCIBus *bus, int bus_num,
|
2021-10-28 07:31:25 +03:00
|
|
|
pci_bus_dev_fn fn,
|
2012-06-21 19:35:28 +04:00
|
|
|
void *opaque);
|
2017-02-22 13:56:53 +03:00
|
|
|
void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
|
2021-10-28 07:31:25 +03:00
|
|
|
pci_bus_dev_fn fn,
|
2017-02-22 13:56:53 +03:00
|
|
|
void *opaque);
|
2021-10-28 07:31:26 +03:00
|
|
|
void pci_for_each_device_under_bus(PCIBus *bus,
|
|
|
|
pci_bus_dev_fn fn, void *opaque);
|
|
|
|
void pci_for_each_device_under_bus_reverse(PCIBus *bus,
|
|
|
|
pci_bus_dev_fn fn,
|
|
|
|
void *opaque);
|
2021-10-28 07:31:25 +03:00
|
|
|
void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
|
|
|
|
pci_bus_fn end, void *parent_state);
|
2015-10-28 09:20:31 +03:00
|
|
|
PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
|
2013-10-14 19:01:07 +04:00
|
|
|
|
|
|
|
/* Use this wrapper when specific scan order is not required. */
|
|
|
|
static inline
|
2021-10-28 07:31:25 +03:00
|
|
|
void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
|
2013-10-14 19:01:07 +04:00
|
|
|
{
|
|
|
|
pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
|
|
|
|
}
|
|
|
|
|
2013-06-06 12:48:48 +04:00
|
|
|
PCIBus *pci_device_root_bus(const PCIDevice *d);
|
2013-06-06 12:48:49 +04:00
|
|
|
const char *pci_root_bus_path(PCIDevice *dev);
|
2021-07-08 15:55:11 +03:00
|
|
|
bool pci_bus_bypass_iommu(PCIBus *bus);
|
2011-01-27 09:56:36 +03:00
|
|
|
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
2010-12-24 06:14:13 +03:00
|
|
|
int pci_qdev_find_device(const char *id, PCIDevice **pdev);
|
2013-09-02 12:37:02 +04:00
|
|
|
void pci_bus_get_w64_range(PCIBus *bus, Range *range);
|
2007-11-17 20:14:51 +03:00
|
|
|
|
2011-01-20 10:21:38 +03:00
|
|
|
void pci_device_deassert_intx(PCIDevice *dev);
|
|
|
|
|
2023-10-17 19:14:04 +03:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers
|
|
|
|
* of a PCIBus
|
|
|
|
*
|
|
|
|
* Allows to modify the behavior of some IOMMU operations of the PCI
|
|
|
|
* framework for a set of devices on a PCI bus.
|
|
|
|
*/
|
|
|
|
typedef struct PCIIOMMUOps {
|
|
|
|
/**
|
|
|
|
* @get_address_space: get the address space for a set of devices
|
|
|
|
* on a PCI bus.
|
|
|
|
*
|
|
|
|
* Mandatory callback which returns a pointer to an #AddressSpace
|
|
|
|
*
|
|
|
|
* @bus: the #PCIBus being accessed.
|
|
|
|
*
|
|
|
|
* @opaque: the data passed to pci_setup_iommu().
|
|
|
|
*
|
|
|
|
* @devfn: device and function number
|
|
|
|
*/
|
|
|
|
AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn);
|
|
|
|
} PCIIOMMUOps;
|
2012-06-27 08:50:45 +04:00
|
|
|
|
2013-08-09 19:09:08 +04:00
|
|
|
AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
|
2023-10-17 19:14:04 +03:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus
|
|
|
|
*
|
|
|
|
* Let PCI host bridges define specific operations.
|
|
|
|
*
|
|
|
|
* @bus: the #PCIBus being updated.
|
|
|
|
* @ops: the #PCIIOMMUOps
|
|
|
|
* @opaque: passed to callbacks of the @ops structure.
|
|
|
|
*/
|
|
|
|
void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque);
|
2012-06-27 08:50:45 +04:00
|
|
|
|
2022-02-17 20:44:50 +03:00
|
|
|
pcibus_t pci_bar_address(PCIDevice *d,
|
|
|
|
int reg, uint8_t type, pcibus_t size);
|
|
|
|
|
2009-06-21 20:50:57 +04:00
|
|
|
static inline void
|
|
|
|
pci_set_byte(uint8_t *config, uint8_t val)
|
|
|
|
{
|
|
|
|
*config = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint8_t
|
2010-01-11 23:20:13 +03:00
|
|
|
pci_get_byte(const uint8_t *config)
|
2009-06-21 20:50:57 +04:00
|
|
|
{
|
|
|
|
return *config;
|
|
|
|
}
|
|
|
|
|
2009-06-21 20:45:30 +04:00
|
|
|
static inline void
|
|
|
|
pci_set_word(uint8_t *config, uint16_t val)
|
|
|
|
{
|
2013-11-05 20:38:29 +04:00
|
|
|
stw_le_p(config, val);
|
2009-06-21 20:45:30 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint16_t
|
2010-01-11 23:20:13 +03:00
|
|
|
pci_get_word(const uint8_t *config)
|
2009-06-21 20:45:30 +04:00
|
|
|
{
|
2013-11-05 20:38:31 +04:00
|
|
|
return lduw_le_p(config);
|
2009-06-21 20:45:30 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
pci_set_long(uint8_t *config, uint32_t val)
|
|
|
|
{
|
2013-11-05 20:38:30 +04:00
|
|
|
stl_le_p(config, val);
|
2009-06-21 20:45:30 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t
|
2010-01-11 23:20:13 +03:00
|
|
|
pci_get_long(const uint8_t *config)
|
2009-06-21 20:45:30 +04:00
|
|
|
{
|
2013-11-05 20:38:32 +04:00
|
|
|
return ldl_le_p(config);
|
2009-06-21 20:45:30 +04:00
|
|
|
}
|
|
|
|
|
2016-06-01 11:23:30 +03:00
|
|
|
/*
|
|
|
|
* PCI capabilities and/or their fields
|
|
|
|
* are generally DWORD aligned only so
|
|
|
|
* mechanism used by pci_set/get_quad()
|
|
|
|
* must be tolerant to unaligned pointers
|
|
|
|
*
|
|
|
|
*/
|
2009-10-30 15:20:59 +03:00
|
|
|
static inline void
|
|
|
|
pci_set_quad(uint8_t *config, uint64_t val)
|
|
|
|
{
|
2016-06-01 11:23:30 +03:00
|
|
|
stq_le_p(config, val);
|
2009-10-30 15:20:59 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t
|
2010-01-11 23:20:13 +03:00
|
|
|
pci_get_quad(const uint8_t *config)
|
2009-10-30 15:20:59 +03:00
|
|
|
{
|
2016-06-01 11:23:30 +03:00
|
|
|
return ldq_le_p(config);
|
2009-10-30 15:20:59 +03:00
|
|
|
}
|
|
|
|
|
2009-01-26 18:37:35 +03:00
|
|
|
static inline void
|
|
|
|
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
|
|
|
|
{
|
2009-06-21 20:45:30 +04:00
|
|
|
pci_set_word(&pci_config[PCI_VENDOR_ID], val);
|
2009-01-26 18:37:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
|
|
|
|
{
|
2009-06-21 20:45:30 +04:00
|
|
|
pci_set_word(&pci_config[PCI_DEVICE_ID], val);
|
2009-01-26 18:37:35 +03:00
|
|
|
}
|
|
|
|
|
2010-02-25 11:41:25 +03:00
|
|
|
static inline void
|
|
|
|
pci_config_set_revision(uint8_t *pci_config, uint8_t val)
|
|
|
|
{
|
|
|
|
pci_set_byte(&pci_config[PCI_REVISION_ID], val);
|
|
|
|
}
|
|
|
|
|
2009-02-01 22:26:20 +03:00
|
|
|
static inline void
|
|
|
|
pci_config_set_class(uint8_t *pci_config, uint16_t val)
|
|
|
|
{
|
2009-06-21 20:45:30 +04:00
|
|
|
pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
|
2009-02-01 22:26:20 +03:00
|
|
|
}
|
|
|
|
|
2010-02-25 11:41:25 +03:00
|
|
|
static inline void
|
|
|
|
pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
|
|
|
|
{
|
|
|
|
pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
|
|
|
|
}
|
|
|
|
|
|
|
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static inline void
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pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
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{
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pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
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}
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2010-10-19 13:06:28 +04:00
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/*
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* helper functions to do bit mask operation on configuration space.
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* Just to set bit, use test-and-set and discard returned value.
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* Just to clear bit, use test-and-clear and discard returned value.
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* NOTE: They aren't atomic.
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*/
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static inline uint8_t
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pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
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{
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uint8_t val = pci_get_byte(config);
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pci_set_byte(config, val & ~mask);
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return val & mask;
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}
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static inline uint8_t
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pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
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{
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uint8_t val = pci_get_byte(config);
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pci_set_byte(config, val | mask);
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return val & mask;
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}
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static inline uint16_t
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pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
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{
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uint16_t val = pci_get_word(config);
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pci_set_word(config, val & ~mask);
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return val & mask;
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}
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static inline uint16_t
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pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
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{
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uint16_t val = pci_get_word(config);
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pci_set_word(config, val | mask);
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return val & mask;
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}
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static inline uint32_t
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pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
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{
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uint32_t val = pci_get_long(config);
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pci_set_long(config, val & ~mask);
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return val & mask;
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}
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static inline uint32_t
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pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
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{
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uint32_t val = pci_get_long(config);
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pci_set_long(config, val | mask);
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return val & mask;
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}
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static inline uint64_t
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pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
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{
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uint64_t val = pci_get_quad(config);
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pci_set_quad(config, val & ~mask);
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return val & mask;
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}
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static inline uint64_t
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pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
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{
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uint64_t val = pci_get_quad(config);
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pci_set_quad(config, val | mask);
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return val & mask;
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}
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2012-02-21 17:41:30 +04:00
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/* Access a register specified by a mask */
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static inline void
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pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
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{
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uint8_t val = pci_get_byte(config);
|
2022-08-18 16:54:21 +03:00
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uint8_t rval;
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assert(mask);
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rval = reg << ctz32(mask);
|
2012-02-21 17:41:30 +04:00
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pci_set_byte(config, (~mask & val) | (mask & rval));
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}
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static inline void
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pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
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|
{
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uint16_t val = pci_get_word(config);
|
2022-08-18 16:54:21 +03:00
|
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|
uint16_t rval;
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assert(mask);
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rval = reg << ctz32(mask);
|
2012-02-21 17:41:30 +04:00
|
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pci_set_word(config, (~mask & val) | (mask & rval));
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}
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static inline void
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pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
|
|
|
|
{
|
|
|
|
uint32_t val = pci_get_long(config);
|
2022-08-18 16:54:21 +03:00
|
|
|
uint32_t rval;
|
|
|
|
|
|
|
|
assert(mask);
|
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|
|
rval = reg << ctz32(mask);
|
2012-02-21 17:41:30 +04:00
|
|
|
pci_set_long(config, (~mask & val) | (mask & rval));
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|
}
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|
static inline void
|
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|
|
pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
|
|
|
|
{
|
|
|
|
uint64_t val = pci_get_quad(config);
|
2022-08-18 16:54:21 +03:00
|
|
|
uint64_t rval;
|
|
|
|
|
|
|
|
assert(mask);
|
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|
|
rval = reg << ctz32(mask);
|
2012-02-21 17:41:30 +04:00
|
|
|
pci_set_quad(config, (~mask & val) | (mask & rval));
|
|
|
|
}
|
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|
|
|
2023-03-04 14:40:43 +03:00
|
|
|
PCIDevice *pci_new_multifunction(int devfn, const char *name);
|
2020-06-10 08:32:02 +03:00
|
|
|
PCIDevice *pci_new(int devfn, const char *name);
|
|
|
|
bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
|
|
|
|
|
2010-06-23 11:15:30 +04:00
|
|
|
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
|
|
|
const char *name);
|
2009-05-15 01:35:07 +04:00
|
|
|
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
|
|
|
|
|
2018-09-19 20:20:57 +03:00
|
|
|
void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
|
2017-02-15 15:18:55 +03:00
|
|
|
|
2013-10-07 11:36:35 +04:00
|
|
|
qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
|
|
|
|
void pci_set_irq(PCIDevice *pci_dev, int level);
|
|
|
|
|
|
|
|
static inline void pci_irq_assert(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
pci_set_irq(pci_dev, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void pci_irq_deassert(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
pci_set_irq(pci_dev, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: PCI does not work this way.
|
|
|
|
* All the callers to this method should be fixed.
|
|
|
|
*/
|
|
|
|
static inline void pci_irq_pulse(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
pci_irq_assert(pci_dev);
|
|
|
|
pci_irq_deassert(pci_dev);
|
|
|
|
}
|
|
|
|
|
2016-07-14 08:56:32 +03:00
|
|
|
MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
|
2021-11-11 16:08:54 +03:00
|
|
|
void pci_set_power(PCIDevice *pci_dev, bool state);
|
2016-07-14 08:56:32 +03:00
|
|
|
|
2007-11-17 20:14:51 +03:00
|
|
|
#endif
|