Added LoongArch32, LoongArch64 machine numbers, which are defined in Microsoft PE SPEC.
[Lionel Debroux: added RISC-V 32, RISC-V 64, RISC-V 128 PE machine numbers as well, since we already have the ARM machine numbers anyway.]
Signed-off-by: Chao Li <lichao@loongson.cn>
Signed-off-by: Lionel Debroux <lionel_debroux@yahoo.fr>
People creating the media through File System Transposition [1] rather than DD
copy may end up with a media that uses a GPT partition table rather than MBR.
So add GPT support to GRUB, as a low cost beneficial change.
For reference, File System Transposition is the default method used by Rufus
and other utilities for creating bootable media from an ISO, and it allows
users to select GPT instead over MBR, in which case memtest86+ will not boot.
[1] https://lists.gnu.org/archive/html/grub-devel/2022-06/msg00024.html
The existing algorithm both read and wrote data beyond the end of the
array and, when moving data, moved it in the wrong direction. Replace
it with a bog-standard insertion sort algorithm. The resulting code
is smaller and probably faster, as memmove() is not in-lined.
* Add a file containing useful macro definitions, currently a single top-level macro for obtaining the size of an array; use it to replace a sizeof(x) / sizeof(x[0]) construct in system/smbus.c . This requires switching the GCC build mode from C11 to C11 with GCC extensions.
* Initial NUMA awareness (#12) support: parse the ACPI SRAT to build up new internal structures related to proximity domains and affinity; use these structures in setup_vm_map() and calculate_chunk() to skip the work on the processors which don't belong to the proximity domain currently being tested.
Tested on a number of 1S single-domain, 2S multi-domain and 4S multi-domain platforms.
SKIP_RANGE(iterations) trick by Martin Whitaker.
This was mentioned in the individual test descriptions in the README,
but easily missed (issue #384). Add a note in the BadRAM section of
the README and also in the error display heading.
* Add boot option to rotate screen display through 90 degrees.
Some machines have a detachable display that can be used in either
portrait or landscape orientations, and require software to rotate
the displayed image accordingly. There is no way to detect the
current orientation through the BIOS, so provide a boot option to
control this. Hopefully we only need to support one (+90 degree)
angle.
Note that the rotate option only works in graphical mode. When booted
by a legacy BIOS using text mode, we have to rely on the BIOS to do
what's necessary.
* Extend boot command line options for display screen control.
Replace "rotate" option with "screen.rhs-up" and "screen.lhs-up" to
allow rotation in either direction. Add a "screen.mode=<w>x<h>"
option to set a preferred width <w> and height <h> for the UEFI
frame buffer. Also allow "screen.mode=bios" to use the default
UEFI frame buffer resolution.
* Add more debug output for EFI frame buffer mode.
* Replicate command line parsing of screen options in efisetup.c.
Trying to do it only once in screen.c didn't work, because static
variables initialied to zero are placed in the bss section, and we
don't zero the bss section until after efisetup() is executed.
The resulting code is in fact smaller, because the compiler can
optimise better when everything is local.
* Add a boot command line option for efisetup debug.
* Improve EFI debug test screen pattern.
* Document the new screen and efidebug boot command line options.
* Fix typo in README.
* Initial commit for ECC support. Preliminary support for AMD Zen.
* Clear ECC registers at startup
* Add config flag (enable_ecc_polling) to toggle ECC polling. (Currently disabled by default for v7 release)
* Optimize the JEP106 list by using __attribute__((packed)) to remove padding. The x86 & x86_64 series support unaligned accesses just fine, after all, and this is not remotely a hot path.
* Optimize several string-related constructs by switching to fixed-length char arrays, which avoids pointers + relocations.
* app/interrupt.c: array of different-length strings, but most of those are lengthy enough for this to be a clear win, especially on x86_64;
* system/usbhcd.c: array of same-length strings;
* tests/tests.h: array of structs containing same-length strings.
* Reduce the size of the list of tests by using a narrower type for the cpu mode, which reduces padding.
* cpuinfo: Add support for Vortex86
Hardcode cache for family 5, use CPUID cache info for family 6.
* cpuinfo: Add support for Vortex86EX
The EX does not have brand string so hardcode name and cache.
* In determine_cache_size(), add an additional test to ensure that only
Vortex86 CPUs are handled, allowing Zhaoxin CPUs to fall through.
Also, remove the no_temperature var to keep only the enable_temperature flag
Older Atom still have the enable_temperature flag hard-coded to false until further tests are done
* Make sure the build workflow actually uses the chosen compiler.
Also clean up the repetitive nature of the workflow by defining the word
size as another matrix axis and making iso the default target.
Signed-off-by: Kimon Hoffmann <Kimon.Hoffmann@lawo.com>
* Disabled clang as a compiler alongside gcc.
The state of the current makefiles/source code is not compatible with
clang, so it makes no sense to try to build with it.
Signed-off-by: Kimon Hoffmann <Kimon.Hoffmann@lawo.com>
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings.
Currently supported platforms:
* Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile)
* AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU).
Individual commits below for archival:
* First functions skeleton for reading IMC/ECC Registers
* Change directory name from 'chipsets' to 'mch' (Memory Controller Hub)
* Add Intel HSW and fix new files encoding
* First Intel HSW IMC implementation
* Add an option to disable MCH registers polling
* Remove old include from Makefiles
* Better Makefile and padding fixes
* Statically init 'imc' struct to generate string relocation record
* Small typos & code fixes
* Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed
* Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core)
* Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer
* Move AMD SMN Registers & offsets to a specific header file
* Add IMC Read support for AMD Zen/Zen2 CPUs
* Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory
* Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13)
* Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer
* Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs
* Various Cleanup #1
Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file
* Various Cleanup 2
* Change DDR5 display format for IMC specs
DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space.
This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
On some modern ULV cores (eg: Gracemont), the 2 following I/O reads to check APIC Timer working status are fused in the frontend, leading to the same value being reported twice and the code falling back to the (unusually disabled on these platforms) PIT timer.
Whether this behavior is intentional or not is unknown.
As usleep/sleep is not available at this point, a dirty delay is added between the two reads.
* cpuinfo: Fix WinChip and Cyrix/NSC CPU name and cache info
Always populate the cache info from extended CPUID, it is not used for
Intel CPUs, even though it is present, and is useful for non-Intel CPUs.
Fix the CPU name and cache sizes for Centaur and Cyrix/NSC CPUs without
brand string, which are the WinChip C6 and all Cyrix CPUs except the
Media GXm.
For the Media GXm and Geode GXm/GXLV/GX1, which are available with both
Cyrix and NSC vendor strings, hardcode the L1 cache size. The Geode GX2
uses standard cache info.
* Add 'Intel' in CPU names for older CPUs
* Add 'Transmeta' and 'IDT' in CPU names for older CPUs
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Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
Lionel Debroux