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0e17f8f195
Bochs/bochs/cpu/cpudb
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Stanislav Shwartsman 0e17f8f195 implemented AMD APIC extensions for SVM support
2012-01-04 16:06:37 +00:00
..
amd_k6_2_chomper.cc added basic (very basic) SVM CPUID into generic_cpuid module 2011-12-28 21:54:51 +00:00
amd_k6_2_chomper.h support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
amd_k6_2_chomper.txt - Fixed compilation issue with cpu-level=5 2011-08-30 22:00:27 +00:00
athlon64_clawhammer.cc fixes for SVN. also turion64_tyler supports RDTSCP - include it in CPUID 2012-01-01 17:54:41 +00:00
athlon64_clawhammer.h support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
athlon64_clawhammer.txt Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 2011-07-31 18:43:46 +00:00
athlon64_venice.cc fixes for SVN. also turion64_tyler supports RDTSCP - include it in CPUID 2012-01-01 17:54:41 +00:00
athlon64_venice.h added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
athlon64_venice.txt added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
atom_n270.cc added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
atom_n270.h added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
atom_n270.txt dos2unix 2011-08-03 17:50:23 +00:00
core2_penryn_t9600.cc added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
core2_penryn_t9600.h added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
core2_penryn_t9600.txt dos2unix for generic_cpuid.cc 2011-08-08 18:20:29 +00:00
core_duo_t2400_yonah.cc added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
core_duo_t2400_yonah.h added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
core_duo_t2400_yonah.txt added yonah CPUID to cpudb. remove bxversion.h from dep files 2011-08-16 19:58:56 +00:00
corei5_arrandale_m520.cc added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
corei5_arrandale_m520.h fixed compilation w/o AVX 2011-10-09 13:56:39 +00:00
corei5_arrandale_m520.txt added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
corei5_lynnfield_750.cc Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
corei5_lynnfield_750.h Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
corei5_lynnfield_750.txt Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
corei7_sandy_bridge_2600K.cc added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
corei7_sandy_bridge_2600K.h added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
corei7_sandy_bridge_2600K.txt Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 2011-07-31 18:43:46 +00:00
Makefile.in Added Corei5 750 (Lynnfield) configuration to the CPUDB 2012-01-02 20:59:02 +00:00
p2_klamath.cc - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 2011-09-25 17:36:20 +00:00
p2_klamath.h - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 2011-09-25 17:36:20 +00:00
p2_klamath.txt Added P2 Klamath CPUID + some code reorg again 2011-08-11 18:06:09 +00:00
p3_katmai.cc - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 2011-09-25 17:36:20 +00:00
p3_katmai.h - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 2011-09-25 17:36:20 +00:00
p3_katmai.txt Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 2011-07-31 18:43:46 +00:00
p4_prescott_celeron_336.cc added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
p4_prescott_celeron_336.h support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
p4_prescott_celeron_336.txt Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 2011-07-31 18:43:46 +00:00
p4_willamette.cc - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 2011-09-25 17:36:20 +00:00
p4_willamette.h - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 2011-09-25 17:36:20 +00:00
p4_willamette.txt Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 2011-07-31 18:43:46 +00:00
pentium_mmx.cc - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 2011-09-25 17:36:20 +00:00
pentium_mmx.h support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
pentium_mmx.txt added pentium mmx to cpudb. for now only can be enabled when cpu-level=5 2011-08-16 19:04:36 +00:00
turion64_tyler.cc implemented AMD APIC extensions for SVM support 2012-01-04 16:06:37 +00:00
turion64_tyler.h added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
turion64_tyler.txt added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00