Stanislav Shwartsman
|
4d10852c04
|
impemented recently published VP2INTERSECTD/Q instructions
|
2019-05-25 19:07:09 +00:00 |
|
Stanislav Shwartsman
|
662b252507
|
added missing endif
|
2019-04-17 16:04:34 +00:00 |
|
Stanislav Shwartsman
|
a022d71774
|
fixed compilation
|
2019-04-14 04:05:04 +00:00 |
|
Stanislav Shwartsman
|
54bdb24e4b
|
remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name
|
2019-02-22 19:15:53 +00:00 |
|
Stanislav Shwartsman
|
3e007fbdea
|
fixed copy-pasted issue with decoding
|
2019-02-17 21:54:38 +00:00 |
|
Stanislav Shwartsman
|
c3f7a34cf5
|
fixed copy-pasted issue with decoding
|
2019-02-17 21:41:45 +00:00 |
|
Stanislav Shwartsman
|
3da93728b3
|
split some opcode reference tables in new decoder between x86-64 and 32 for better perf
|
2019-02-17 21:22:54 +00:00 |
|
Stanislav Shwartsman
|
cd79d22113
|
fixes for 32-bit mode only compilation
|
2019-02-16 19:42:04 +00:00 |
|
Stanislav Shwartsman
|
4f625b23e0
|
enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore
|
2019-02-16 15:23:24 +00:00 |
|
Stanislav Shwartsman
|
61dcc4ace7
|
remove unreferenced decode table
|
2019-01-29 13:44:39 +00:00 |
|
Stanislav Shwartsman
|
f8ec18acd5
|
fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes
|
2019-01-27 18:52:03 +00:00 |
|
Stanislav Shwartsman
|
0b18a42e4e
|
fixed decoding of AVX-512 opcodes
|
2019-01-27 17:35:21 +00:00 |
|
Stanislav Shwartsman
|
5cb4639891
|
fixed decoding of AVX-512 opcodes
|
2019-01-27 17:31:28 +00:00 |
|
Stanislav Shwartsman
|
6dc5cfe80b
|
fixed typo in opcode name
|
2019-01-24 20:10:46 +00:00 |
|
Stanislav Shwartsman
|
af75c2a81e
|
fixed comment in the opcode table for EVEX
|
2019-01-22 18:31:39 +00:00 |
|
Stanislav Shwartsman
|
9bc7faf493
|
dump all supported CPU fetures into Bochs log from CPUID object
|
2019-01-05 20:17:39 +00:00 |
|
Stanislav Shwartsman
|
fcd9ce1634
|
fix compilation without x86_64
|
2018-04-15 14:22:16 +00:00 |
|
Stanislav Shwartsman
|
d000e21001
|
added MOVDIRI opcode implementation
|
2018-04-06 05:06:36 +00:00 |
|
Stanislav Shwartsman
|
fd15b61d94
|
keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM
|
2018-04-04 19:31:56 +00:00 |
|
Stanislav Shwartsman
|
8c9f7f54b6
|
update CPUID definitions with recently published EAS-33 extensions document
|
2018-04-04 18:15:44 +00:00 |
|
Stanislav Shwartsman
|
0cd49ddae4
|
fixed compilation with EVEX disabled
|
2018-03-29 08:50:38 +00:00 |
|
Stanislav Shwartsman
|
773f1b7e42
|
cleanup return value of all instruction handlers
|
2018-02-16 07:57:32 +00:00 |
|
Stanislav Shwartsman
|
769ed3ef88
|
fixed MOVBE instruction decoding
|
2018-01-23 19:53:34 +00:00 |
|
Stanislav Shwartsman
|
3c08cfedf2
|
fixed buffer overflow when printing instruction disasm for opcode bytes which cannot be decoded
|
2017-12-31 21:22:04 +00:00 |
|
Stanislav Shwartsman
|
6566cab8aa
|
fixed new disasm for avx2 opcodes
|
2017-12-30 18:45:21 +00:00 |
|
Stanislav Shwartsman
|
4c03fe3e2c
|
fixed disasm of vcvtps2ph/ph2ps opcodes
|
2017-12-28 19:59:42 +00:00 |
|
Stanislav Shwartsman
|
ed8fa8ac61
|
fix compilation with no AVX enabled
|
2017-12-24 15:38:21 +00:00 |
|
Stanislav Shwartsman
|
ca034f0642
|
fixed disasm of sse insertps instruction
|
2017-12-21 18:18:10 +00:00 |
|
Stanislav Shwartsman
|
59c542fb06
|
fix disasm of FISTTP opcodes
|
2017-12-19 20:36:55 +00:00 |
|
Stanislav Shwartsman
|
4337a062e2
|
disasm memsize for gather opcodes
|
2017-12-19 19:51:55 +00:00 |
|
Stanislav Shwartsman
|
15187110ef
|
implement disasm of implicit memory reference for maskmovdqu/maskmovq opcodes. fix vmaskmovdqu disasm for legacy disasm as well
|
2017-12-19 19:45:30 +00:00 |
|
Stanislav Shwartsman
|
e086f7ba19
|
split INSERTPS opcode to reg and mem forms
|
2017-12-19 19:25:40 +00:00 |
|
Stanislav Shwartsman
|
ce3eafa535
|
disasm fix
|
2017-12-17 18:47:21 +00:00 |
|
Stanislav Shwartsman
|
79ec183ff6
|
fixup for MMX opcodes disasm
|
2017-12-17 17:21:02 +00:00 |
|
Stanislav Shwartsman
|
5dc5e01a12
|
disasm fixes and reorg of pinsr* opcodes
|
2017-12-16 18:34:20 +00:00 |
|
Stanislav Shwartsman
|
6a4e8ff2f1
|
fixed typo in prev commit
|
2017-12-13 21:08:10 +00:00 |
|
Stanislav Shwartsman
|
f362f34ed6
|
correctly decode PINSRQ instruction
|
2017-12-13 20:59:41 +00:00 |
|
Stanislav Shwartsman
|
50a799ea11
|
split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction
|
2017-12-13 20:18:59 +00:00 |
|
Stanislav Shwartsman
|
07bff3be43
|
fixed decoding of VPINSRB/W/D/Q and VINSERTPS with EVEX prefix
|
2017-12-13 20:02:12 +00:00 |
|
Stanislav Shwartsman
|
8a311515dd
|
correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only
fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
|
2017-12-13 19:51:25 +00:00 |
|
Stanislav Shwartsman
|
2f3c9d3c8c
|
correct disasm for movsxd opcode
|
2017-12-13 18:44:13 +00:00 |
|
Stanislav Shwartsman
|
c1dc514c2a
|
clarify disasm of movlhps/movhlps opcodes
|
2017-12-12 08:55:09 +00:00 |
|
Stanislav Shwartsman
|
fd953421f4
|
new disasm: add correct memaccess size for FLDCW
|
2017-12-11 19:58:09 +00:00 |
|
Stanislav Shwartsman
|
a84d9cf1c7
|
disasm: fix crc32 operand description
|
2017-12-11 19:45:50 +00:00 |
|
Stanislav Shwartsman
|
a028ef7c9c
|
bugfix for decoder with EVEX enabled
|
2017-12-11 19:29:11 +00:00 |
|
Stanislav Shwartsman
|
e46f37b40e
|
fixed disasm of memsize for sse legacy instructions
|
2017-12-11 18:33:33 +00:00 |
|
Stanislav Shwartsman
|
404a5f2c53
|
bugfix for previous commit
|
2017-12-11 16:41:48 +00:00 |
|
Stanislav Shwartsman
|
b03f78d652
|
updates for bochs decoder and decoder based disasm
|
2017-12-11 15:45:43 +00:00 |
|
Stanislav Shwartsman
|
c80e587ded
|
properly handle kmask registers in modrm form
|
2017-12-05 19:33:23 +00:00 |
|
Stanislav Shwartsman
|
8f15cfb514
|
fixed link err with debugger enabled
|
2017-12-05 19:23:41 +00:00 |
|