Commit Graph

13642 Commits

Author SHA1 Message Date
Volker Ruppert
f5717a9340 Added some documentation for the VBE memory size option. 2024-11-03 21:36:23 +01:00
Volker Ruppert
c511f3f270 Added VBE memory size option (requires latest VGABIOS).
Setting VBE memory size to 4, 8, 16 and 32 MB is now possible. Since a memory
size change can also change the number of available modes and the value for
"number of image pages" in the mode info it is required to use the latest
VGABIOS binary.
Related changes:
- Make sure the VBE entry appears at index 1 of VGA extension option list.
- Removed all memory size constants and use BX_VGA_THIS s.memsize instead.

TODO: Remove the static mode info table and create it dynamicly similar to
      Banshee and Cirrus.
2024-11-03 19:44:55 +01:00
Volker Ruppert
8562c955bf Updated LGPL'd VGABIOS from GitHub repository.
This change is required for implementing VBE memory size option.
New official release of the LGPL'd VGABIOS coming soon.
2024-11-03 19:11:49 +01:00
Stanislav Shwartsman
c09656db29 according to SDM for VSCALEF* instructions, denormal is not reported for Src2 2024-11-01 18:42:48 +02:00
Stanislav Shwartsman
b1ea77be65 update comment for min/max functions in softfloat3e 2024-11-01 15:59:25 +02:00
Volker Ruppert
87eeb9dcfa Cirrus: In text mode always use the standard VGA update code. 2024-10-31 18:52:09 +01:00
Stanislav Shwartsman
47b05e55e1 revert lock handling change
after checking agains Intel reference decoder (Xed) it shown few mismatches.
The mismatches are not functionally important - some very long instructions with lock prefix would cause #UD (due to badly placed lock prefix) insetad of #GP due to excessive opcode length
Seems like Xed evaluates entire instruction to the end and only then converts it to #UD due to lock prefix
2024-10-30 06:18:46 +02:00
Volker Ruppert
2ddb701433 Cirrus: Fixed lags caused by incorrect redraw value for backward BitBlt. 2024-10-29 22:00:36 +01:00
Stanislav Shwartsman
42e7c31e93 fixed typo 2024-10-29 07:31:27 +02:00
Stanislav Shwartsman
94df2e8694 change the way lock prefix is handled in Bochs decoder
this solves issue with ALT_MOV_CR0 AMD's feature (where lock mov cr0 is treated as mov cr8)
and also speeds up decoding a bit
2024-10-28 23:00:17 +02:00
Stanislav Shwartsman
ce839132ab rename all EVEX opcodes from BX_IA_V512_* to BX_IA_EVEX_*
they are EVEX not necessary V512
2024-10-28 20:28:53 +02:00
Stanislav Shwartsman
52a39639f0 enable x86 debugger extensions by default 2024-10-28 18:47:25 +02:00
Stanislav Shwartsman
052a2c640d add missing \n 2024-10-27 07:42:21 +02:00
Stanislav Shwartsman
dc7de097b8 simplify code for AVX-512 masked merges 2024-10-26 23:49:04 +03:00
Stanislav Shwartsman
884d8983eb rename/simplify names of BF16 instruction handlers 2024-10-26 22:26:13 +03:00
Stanislav Shwartsman
8d1f2e1731 simplify prepare_ne_softfloat_status_helper function 2024-10-26 18:33:55 +03:00
Stanislav Shwartsman
2a9ff9e959 opcode naming style fix 2024-10-26 14:40:27 +03:00
Stanislav Shwartsman
056e1c52bf fixed disasm of VDPBF16PS instruction 2024-10-26 14:25:08 +03:00
Stanislav Shwartsman
a80bcba55d VDBPSADBW must be encoded with EVEX.W0 2024-10-26 14:11:00 +03:00
Stanislav Shwartsman
747f703bd8 fixed decoding of AVX-VNNI-INT8 instructions
instructions VPDPBSSDS and VPDPBSUDS were swapped in decoder tables
2024-10-26 10:16:11 +03:00
Stanislav Shwartsman
50c505224f unify handlers for VCOMISH and VUCOMISH instructions 2024-10-26 09:25:27 +03:00
Volker Ruppert
a94ebf9990 BIOS workaround to fix network boot after adding USB boot option in Bochs.
CHANGES: removed duplicate line.
2024-10-24 23:33:00 +02:00
Stanislav Shwartsman
b3bd4a7eca simplify AMD CPUDB definitions reusing generic function for leaf 0x80000001.ECX
remove specialized function from bx_generic cpuid
add some basics cpuid sanity checks from bx_generic
next step: to remove entire bx_generic cpuid
2024-10-24 21:39:57 +03:00
Stanislav Shwartsman
80019a34c0 Support for disabling of one of more CPU feature from CPUID configuration (see "exclude_features" in bochsrc sample and documentation) 2024-10-24 20:48:53 +03:00
Stanislav Shwartsman
39414b6e62 more updates to CHANGES 2024-10-24 20:20:14 +03:00
Volker Ruppert
bb90786fca Update CHANGES. 2024-10-24 18:18:33 +02:00
Benjamin David Lunt
8fda7423d3
Allow the boot usb option (#209)
This allows the `usb` option to be used in the `boot:` parameter. Of
course there is not support for booting from a USB, but this allows for
a (probably much) further down the road addition.

This will break the current bios when booting from a network. However,
the bios is already broken in this manner, especially when
`BX_ELTORITO_BOOT` is not defined. The current bios code assumes and
hard codes the BEV entry to 4. However, if the `BX_ELTORITO_BOOT` define
is missing, the BEV will be added to the third entry, not the fourth
entry.

For the BIOS to be updated correctly, things like the following will
need to be updated instead of hard coded to `[4]`.

54961f0326/bochs/bios/rombios.c (L2205)

The following will need to be not hard coded to 4.

54961f0326/bochs/bios/rombios.c (L2253-L2257)

The following will need "usb" added.

54961f0326/bochs/bios/rombios.c (L2102)

The following assumes the next entry will be the fourth entry, not
checking to see if `BX_ELTORITO_BOOT` was defined.

54961f0326/bochs/bios/rombios.c (L10851-L10857)

The following comment will need to be updated.

54961f0326/bochs/bios/rombios.c (L8365-L8371)

As well as a few other fixes and updates.

This PR simply allows the value of '4' (`BX_BOOT_USB`) to be placed in
the boot sequence options, moving the network (`BX_BOOT_NETWORK`) to the
next number.

The boot sequence option still only allows three parameters.
`boot: cdrom, floppy, disk`
or
`boot: cdrom, usb, disk`
I don't think it is necessary to add a fourth.

---------

Co-authored-by: Volker Ruppert <Volker.Ruppert@t-online.de>
2024-10-24 17:02:07 +02:00
Volker Ruppert
15badf06c4 Preparing Bochs code for accepting USB boot option PR.
The current code would panic if booting from network is selected.
Added two empty items for PCMCIA and USB as a workaround.
FIXME 1: The config interfaces win32paramdialog and wxdialog now showing
         two empty lines in combo box.
FIXME 2: The Bochs BIOS can only boot from network if selected in boot menu
         (press F12).
2024-10-24 16:48:43 +02:00
Volker Ruppert
7373c19c78 Banshee: added host-to-screen stretching BitBlt support (#365). 2024-10-24 10:07:51 +02:00
Stanislav Shwartsman
556f64b8e7 extract EVEX opcodes definitions to separate file ia_opcodes_evex.def 2024-10-23 21:34:03 +03:00
Stanislav Shwartsman
7368a56647 remove duplicate print of eflags in debugger 2024-10-23 16:19:47 +03:00
Stanislav Shwartsman
c015c8168c fixed TPAUSE implementation and close issue #366 2024-10-23 15:02:54 +03:00
Stanislav Shwartsman
cbb1e0ed8e updated CHANGES 2024-10-23 14:34:29 +03:00
Stanislav Shwartsman
93a07982d5 rewritten LASS implementation to fix failures under ArrowLake model
biggest issue was:
A supervisor-mode data access causes a LASS violation only if supervisor-mode access protection is enabled
(CR4.SMAP = 1) and RFLAGS.AC = 0 or the access implicitly accesses a system data structure
2024-10-23 14:30:44 +03:00
Stanislav Shwartsman
a4c47d9559 added helper function to stringify EFLAGS as well and reuse it in Bochs debugger 2024-10-23 12:43:50 +03:00
Stanislav Shwartsman
2dfdd98ccf improve debug print after simulation finishes
add detailed print for CR0, CR4, XCR0 and EFER extensions
2024-10-23 12:15:02 +03:00
Stanislav Shwartsman
36b9cd93cf enable more bits in MSR IA32_SPEC_CTRL to support Win11 boot in Sapphire Rapids and Arrow Lake CPU models 2024-10-23 11:14:23 +03:00
Stanislav Shwartsman
d69acea2c0 fix name of the processor in the warning message 2024-10-23 10:48:24 +03:00
Stanislav Shwartsman
f90201b603 added ArrowLake CPU definition
features: AVX-VNNI, AVX-IFMA, AVX-VNNI-INT8, AVX-VNNI-INT16, AVX_NE_CONVERT, GFNI, VAES/VPCLMULQDQ, SHA512, SM3/SM4, CMPCCXADD, LASS, SERIALIZE, UINTR
update CHANGES
2024-10-23 10:20:23 +03:00
Stanislav Shwartsman
5c81b532a2 opcodes with EVEX.LLIG could come with any VL value and still will be allowed on AVX10.VL256 only machine 2024-10-22 23:27:00 +03:00
Stanislav Shwartsman
1f6436499d add AVX10.256 emulation VMX control 2024-10-22 22:15:41 +03:00
Stanislav Shwartsman
6717e8255d add XSAVE/XRSTOR support for AVX10.256 2024-10-22 21:43:57 +03:00
Stanislav Shwartsman
8469fcade1 make assignHandler member function for cleaner code 2024-10-22 21:09:16 +03:00
Stanislav Shwartsman
5bff389409 fix complation with minimalistic configuration which has no CPUID yet 2024-10-22 20:55:33 +03:00
Stanislav Shwartsman
60f8ab2a36 add preliminary AVX10.1 handling
AVX10.1 includes the following AVX extensions:
	x86_feature(BX_ISA_AVX512, "avx512")                                    /* AVX-512 instruction */
	x86_feature(BX_ISA_AVX512_DQ, "avx512dq")                               /* AVX-512DQ instruction */
	x86_feature(BX_ISA_AVX512_BW, "avx512bw")                               /* AVX-512 Byte/Word instruction */
	x86_feature(BX_ISA_AVX512_CD, "avx512cd")                               /* AVX-512 Conflict Detection instruction */
	x86_feature(BX_ISA_AVX512_VBMI, "avx512vbmi")                           /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
	x86_feature(BX_ISA_AVX512_VBMI2, "avx512vbmi2")                         /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
	x86_feature(BX_ISA_AVX512_IFMA52, "avx512ifma52")                       /* AVX-512 IFMA52 Instructions */
	x86_feature(BX_ISA_AVX512_VPOPCNTDQ, "avx512vpopcnt")                   /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
	x86_feature(BX_ISA_AVX512_VNNI, "avx512vnni")                           /* AVX-512 VNNI Instructions */
	x86_feature(BX_ISA_AVX512_BITALG, "avx512bitalg")                       /* AVX-512 BITALG Instructions */
	x86_feature(BX_ISA_AVX512_BF16, "avx512bf16")                           /* AVX-512 BF16 Instructions */
	x86_feature(BX_ISA_AVX512_FP16, "avx512fp16")                           /* AVX-512 FP16 Instructions */

And it could be handling 256-bit only, in this case avx10_1 will be enabled but avx10_vl512 will not.
Bochs will support all relevant instructions but without 512 bit mode in this case, attemp to encode VL512 in EVEX will result in #UD
also added support for AVX10 CPUID leaf 0x24

TODO: VMX support
2024-10-22 20:44:46 +03:00
Stanislav Shwartsman
3db8404a03 correctly report CPUID leafs 0x19-0x1c as reserved on Sappire Rapids CPUID with AMX enabled 2024-10-22 12:51:14 +03:00
Cacodemon345
f6617f29d6
UHCI: do not deactivate TDs on NAKs (#362)
NAKs from USB devices do not deactivate TDs according to the official
UHCI spec (page 22).

Reference: http://ftp.netbsd.org/pub/NetBSD/misc/blymn/uhci11d.pdf
2024-10-21 16:10:19 +02:00
Volker Ruppert
ffb3b43268 Cirrus: Fixed banking and hardware cursor in VGA compatible modes. 2024-10-20 19:44:14 +02:00
Volker Ruppert
d5e89aa731 Cirrus: Fixed uninitialized variable. 2024-10-20 16:32:47 +02:00
Stanislav Shwartsman
8c053ca361 added initial code for AMX_MOVRS instructions 2024-10-20 11:08:58 +03:00