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added initial code for AMX_MOVRS instructions

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This commit is contained in:
Stanislav Shwartsman 2024-10-20 11:08:58 +03:00
parent 3de88be5ac
commit 8c053ca361
4 changed files with 15 additions and 4 deletions
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5
bochs/cpu/cpuid.cc
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@ -354,8 +354,13 @@ void bx_cpuid_t::get_std_cpuid_amx_tmul_leaf(Bit32u subfunction, cpuid_function_
leaf->eax |= BX_CPUID_AMX_EXTENSIONS_EAX_AMX_COMPLEX;
if (is_cpu_extension_supported(BX_ISA_AMX_FP16))
leaf->eax |= BX_CPUID_AMX_EXTENSIONS_EAX_AMX_FP16;
// AMX_FP8
// AMX_TRANSPOSE
if (is_cpu_extension_supported(BX_ISA_AMX_TF32))
leaf->eax |= BX_CPUID_AMX_EXTENSIONS_EAX_AMX_TF32;
// AMX_AVX512
if (is_cpu_extension_supported(BX_ISA_AMX_MOVRS))
leaf->eax |= BX_CPUID_AMX_EXTENSIONS_EAX_AMX_MOVRS;
// EBX/ECX/EDX = 0 (reserved)
break;

1
bochs/cpu/decoder/features.h
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@ -118,6 +118,7 @@ x86_feature(BX_ISA_AMX_BF16, "amx_bf16") /* AMX-B
x86_feature(BX_ISA_AMX_FP16, "amx_fp16") /* AMX-FP16 Instructions */
x86_feature(BX_ISA_AMX_TF32, "amx_tf32") /* AMX-TF32 Instructions */
x86_feature(BX_ISA_AMX_COMPLEX, "amx_complex") /* AMX-COMPLEX Instructions */
x86_feature(BX_ISA_AMX_MOVRS, "amx_movrs") /* AMX-MOVRS Instructions */
x86_feature(BX_ISA_XAPIC, "xapic") /* XAPIC support */
x86_feature(BX_ISA_X2APIC, "x2apic") /* X2APIC support */
x86_feature(BX_ISA_XAPIC_EXT, "xapicext") /* XAPIC Extensions support (AMD) */

11
bochs/cpu/decoder/fetchdecode_avx.h
View File

@ -1006,6 +1006,11 @@ static const Bit64u BxOpcodeGroup_VEX_0F3849[] = {
last_opcode(ATTR_SSE_PREFIX_F2 | ATTR_VEX_W0 | ATTR_VL128 | ATTR_RRR0 | ATTR_MODC0 | ATTR_IS64, BX_IA_TILEZERO_Tnnn)
};
static const Bit64u BxOpcodeGroup_VEX_0F384A[] = {
form_opcode(ATTR_SSE_PREFIX_66 | ATTR_VEX_W0 | ATTR_VL128 | ATTR_MOD_MEM | ATTR_IS64, BX_IA_TILELOADDRST1_TnnnMdq),
last_opcode(ATTR_SSE_PREFIX_F2 | ATTR_VEX_W0 | ATTR_VL128 | ATTR_MOD_MEM | ATTR_IS64, BX_IA_TILELOADDRS_TnnnMdq)
};
static const Bit64u BxOpcodeGroup_VEX_0F384B[] = {
form_opcode(ATTR_SSE_PREFIX_66 | ATTR_VEX_W0 | ATTR_VL128 | ATTR_MOD_MEM | ATTR_IS64, BX_IA_TILELOADDT1_TnnnMdq),
form_opcode(ATTR_SSE_PREFIX_F3 | ATTR_VEX_W0 | ATTR_VL128 | ATTR_MOD_MEM | ATTR_IS64, BX_IA_TILESTORED_MdqTnnn),
@ -1931,14 +1936,12 @@ static const Bit64u *BxOpcodeTableVEX[256*3] = {
#if BX_SUPPORT_AMX
/* 48 */ ( BxOpcodeGroup_VEX_0F3848 ),
/* 49 */ ( BxOpcodeGroup_VEX_0F3849 ),
/* 4A */ ( BxOpcodeGroup_VEX_0F384A ),
/* 4B */ ( BxOpcodeGroup_VEX_0F384B ),
#else
/* 48 */ ( BxOpcodeGroup_ERR ),
/* 49 */ ( BxOpcodeGroup_ERR ),
#endif
/* 4A */ ( BxOpcodeGroup_ERR ),
#if BX_SUPPORT_AMX
/* 4B */ ( BxOpcodeGroup_VEX_0F384B ),
#else
/* 4B */ ( BxOpcodeGroup_ERR ),
#endif
/* 4C */ ( BxOpcodeGroup_ERR ),

2
bochs/cpu/decoder/ia_opcodes.def
View File

@ -2765,6 +2765,8 @@ bx_define_opcode(BX_IA_LDTILECFG, "ldtilecfg", "ldtilecfg", &BX_CPU_C::LDTILECFG
bx_define_opcode(BX_IA_STTILECFG, "sttilecfg", "sttilecfg", &BX_CPU_C::STTILECFG, NULL, BX_ISA_AMX, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_PREPARE_AMX)
bx_define_opcode(BX_IA_TILELOADD_TnnnMdq, "tileloadd", "tileloadd", &BX_CPU_C::TILELOADD_TnnnMdq, NULL, BX_ISA_AMX, OP_Tnnn, OP_M, OP_NONE, OP_NONE, BX_PREPARE_AMX)
bx_define_opcode(BX_IA_TILELOADDT1_TnnnMdq, "tileloaddt1", "tileloaddt1", &BX_CPU_C::TILELOADD_TnnnMdq, NULL, BX_ISA_AMX, OP_Tnnn, OP_M, OP_NONE, OP_NONE, BX_PREPARE_AMX)
bx_define_opcode(BX_IA_TILELOADDRS_TnnnMdq, "tileloaddrs", "tileloaddrs", &BX_CPU_C::TILELOADD_TnnnMdq, NULL, BX_ISA_AMX_MOVRS, OP_Tnnn, OP_M, OP_NONE, OP_NONE, BX_PREPARE_AMX)
bx_define_opcode(BX_IA_TILELOADDRST1_TnnnMdq, "tileloaddrst1", "tileloaddrst1", &BX_CPU_C::TILELOADD_TnnnMdq, NULL, BX_ISA_AMX_MOVRS, OP_Tnnn, OP_M, OP_NONE, OP_NONE, BX_PREPARE_AMX)
bx_define_opcode(BX_IA_TILESTORED_MdqTnnn, "tilestored", "tilestored", &BX_CPU_C::TILESTORED_MdqTnnn, NULL, BX_ISA_AMX, OP_M, OP_Tnnn, OP_NONE, OP_NONE, BX_PREPARE_AMX)
bx_define_opcode(BX_IA_TILERELEASE, "tilerelease", "tilerelease", NULL, &BX_CPU_C::TILERELEASE, BX_ISA_AMX, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_PREPARE_AMX)
bx_define_opcode(BX_IA_TILEZERO_Tnnn, "tilezero", "tilezero", NULL, &BX_CPU_C::TILEZERO_Tnnn, BX_ISA_AMX, OP_Tnnn, OP_NONE, OP_NONE, OP_NONE, BX_PREPARE_AMX)