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simplify AMD CPUDB definitions reusing generic function for leaf 0x80000001.ECX

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remove specialized function from bx_generic cpuid
add some basics cpuid sanity checks from bx_generic
next step: to remove entire bx_generic cpuid
This commit is contained in:
Stanislav Shwartsman 2024-10-24 21:30:10 +03:00
parent 80019a34c0
commit b3bd4a7eca
22 changed files with 124 additions and 174 deletions
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18
bochs/cpu/cpudb/amd/phenomx3_8650_toliman.cc
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@ -307,20 +307,10 @@ void phenom_8650_toliman_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [22:22] TBM: trailing bit manipulation instructions support
// [23:23] Topology extensions support
// [31:24] Reserved
leaf->ecx = BX_CPUID_EXT1_ECX_LAHF_SAHF |
BX_CPUID_EXT1_ECX_CMP_LEGACY |
#if BX_SUPPORT_SVM
BX_CPUID_EXT1_ECX_SVM |
#endif
BX_CPUID_EXT1_ECX_EXT_APIC_SPACE |
BX_CPUID_EXT1_ECX_ALT_MOV_CR8 |
BX_CPUID_EXT1_ECX_LZCNT |
BX_CPUID_EXT1_ECX_SSE4A |
BX_CPUID_EXT1_ECX_MISALIGNED_SSE |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
BX_CPUID_EXT1_ECX_IBS;
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_CMP_LEGACY |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
BX_CPUID_EXT1_ECX_IBS);
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 for AMD

39
bochs/cpu/cpudb/amd/ryzen.cc
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@ -409,7 +409,7 @@ void ryzen_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [14:14] Reserved
// [15:15] LWP: Light weight profiling
// [16:16] FMA4: Four-operand FMA instructions support
// * [17:17] Translation Cache Extensions
// * [17:17] TCE: Translation Cache Extensions
// [18:18] Reserved
// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
// [20:20] Reserved
@ -422,32 +422,19 @@ void ryzen_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280
// * [28:28] PerfCtrExtL2I: L2I performance counter extensions support
// * [29:29] MONITORX/MWAITX instructions support
// [30:30] Reserved
// [30:30] AddrMaskExt: address mask extension support for instruction breakpoint
// [31:31] Reserved
leaf->ecx = BX_CPUID_EXT1_ECX_LAHF_SAHF |
BX_CPUID_EXT1_ECX_CMP_LEGACY |
#if BX_SUPPORT_SVM
BX_CPUID_EXT1_ECX_SVM |
#endif
BX_CPUID_EXT1_ECX_EXT_APIC_SPACE |
BX_CPUID_EXT1_ECX_ALT_MOV_CR8 |
BX_CPUID_EXT1_ECX_LZCNT |
BX_CPUID_EXT1_ECX_SSE4A |
BX_CPUID_EXT1_ECX_MISALIGNED_SSE |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
/* BX_CPUID_EXT1_ECX_SKINIT | */ // not implemented
BX_CPUID_EXT1_ECX_WDT |
BX_CPUID_EXT1_ECX_TCE |
BX_CPUID_EXT1_ECX_TOPOLOGY_EXTENSIONS |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_CORE |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_NB |
BX_CPUID_EXT1_ECX_DATA_BREAKPOINT_EXT |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_L2I |
#if BX_SUPPORT_MONITOR_MWAIT
BX_CPUID_EXT1_ECX_MONITORX_MWAITX |
#endif
0;
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_CMP_LEGACY |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
/* BX_CPUID_EXT1_ECX_SKINIT | */ // not implemented
BX_CPUID_EXT1_ECX_WDT |
BX_CPUID_EXT1_ECX_TCE |
BX_CPUID_EXT1_ECX_TOPOLOGY_EXTENSIONS |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_CORE |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_NB |
BX_CPUID_EXT1_ECX_DATA_BREAKPOINT_EXT |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_L2I);
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 for AMD

40
bochs/cpu/cpudb/amd/trinity_apu.cc
View File

@ -379,7 +379,7 @@ void trinity_apu_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [14:14] Reserved
// * [15:15] LWP: Light weight profiling
// * [16:16] FMA4: Four-operand FMA instructions support
// * [17:17] Translation Cache Extensions
// * [17:17] TCE: Translation Cache Extensions
// [18:18] Reserved
// * [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
// [20:20] Reserved
@ -388,31 +388,19 @@ void trinity_apu_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// * [23:23] PerfCtrExtCore: core perf counter extensions support
// * [24:24] PerfCtrExtNB: NB perf counter extensions support
// [31:25] Reserved
leaf->ecx = BX_CPUID_EXT1_ECX_LAHF_SAHF |
BX_CPUID_EXT1_ECX_CMP_LEGACY |
#if BX_SUPPORT_SVM
BX_CPUID_EXT1_ECX_SVM |
#endif
BX_CPUID_EXT1_ECX_EXT_APIC_SPACE |
BX_CPUID_EXT1_ECX_ALT_MOV_CR8 |
BX_CPUID_EXT1_ECX_LZCNT |
BX_CPUID_EXT1_ECX_SSE4A |
BX_CPUID_EXT1_ECX_MISALIGNED_SSE |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
BX_CPUID_EXT1_ECX_IBS |
BX_CPUID_EXT1_ECX_XOP |
/* BX_CPUID_EXT1_ECX_SKINIT | */ // not implemented
BX_CPUID_EXT1_ECX_WDT |
/* BX_CPUID_EXT1_ECX_LWP | */ // not implemented
BX_CPUID_EXT1_ECX_FMA4 |
BX_CPUID_EXT1_ECX_TCE |
BX_CPUID_EXT1_ECX_NODEID |
BX_CPUID_EXT1_ECX_TBM |
BX_CPUID_EXT1_ECX_TOPOLOGY_EXTENSIONS |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_CORE |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_NB;
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_CMP_LEGACY |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
BX_CPUID_EXT1_ECX_IBS |
BX_CPUID_EXT1_ECX_XOP |
/* BX_CPUID_EXT1_ECX_SKINIT | */ // not implemented
BX_CPUID_EXT1_ECX_WDT |
/* BX_CPUID_EXT1_ECX_LWP | */ // not implemented
BX_CPUID_EXT1_ECX_TCE |
BX_CPUID_EXT1_ECX_NODEID |
BX_CPUID_EXT1_ECX_TOPOLOGY_EXTENSIONS |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_CORE |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_NB);
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 for AMD

31
bochs/cpu/cpudb/amd/zambezi.cc
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@ -342,27 +342,16 @@ void zambezi_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// * [23:23] PerfCtrExtCore: core perf counter extensions support
// * [24:24] PerfCtrExtNB: NB perf counter extensions support
// [31:25] Reserved
leaf->ecx = BX_CPUID_EXT1_ECX_LAHF_SAHF |
BX_CPUID_EXT1_ECX_CMP_LEGACY |
#if BX_SUPPORT_SVM
BX_CPUID_EXT1_ECX_SVM |
#endif
BX_CPUID_EXT1_ECX_EXT_APIC_SPACE |
BX_CPUID_EXT1_ECX_ALT_MOV_CR8 |
BX_CPUID_EXT1_ECX_LZCNT |
BX_CPUID_EXT1_ECX_SSE4A |
BX_CPUID_EXT1_ECX_MISALIGNED_SSE |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
BX_CPUID_EXT1_ECX_IBS |
BX_CPUID_EXT1_ECX_XOP |
BX_CPUID_EXT1_ECX_WDT |
BX_CPUID_EXT1_ECX_FMA4 |
BX_CPUID_EXT1_ECX_NODEID |
BX_CPUID_EXT1_ECX_TOPOLOGY_EXTENSIONS |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_CORE |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_NB;
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_CMP_LEGACY |
BX_CPUID_EXT1_ECX_PREFETCHW |
BX_CPUID_EXT1_ECX_OSVW |
BX_CPUID_EXT1_ECX_IBS |
BX_CPUID_EXT1_ECX_XOP |
BX_CPUID_EXT1_ECX_WDT |
BX_CPUID_EXT1_ECX_NODEID |
BX_CPUID_EXT1_ECX_TOPOLOGY_EXTENSIONS |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_CORE |
BX_CPUID_EXT1_ECX_PERFCTR_EXT_NB);
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 for AMD

2
bochs/cpu/cpudb/intel/arrow_lake.cc
View File

@ -777,7 +777,7 @@ void arrow_lake_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/broadwell_ult.cc
View File

@ -555,7 +555,7 @@ void broadwell_ult_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [29:29] Reserved
// [30:30] Reserved
// [31:31] Reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/core2_penryn_t9600.cc
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@ -426,7 +426,7 @@ void core2_penryn_t9600_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel();
leaf->ecx = get_ext_cpuid_leaf_1_ecx();
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei3_cnl.cc
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@ -612,7 +612,7 @@ void corei3_cnl_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280
// [28:28] PerfCtrExtL2I: L2I performance counter extensions support
// [31:29] Reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei5_arrandale_m520.cc
View File

@ -446,7 +446,7 @@ void corei5_arrandale_m520_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel();
leaf->ecx = get_ext_cpuid_leaf_1_ecx();
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei5_lynnfield_750.cc
View File

@ -424,7 +424,7 @@ void corei5_lynnfield_750_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel();
leaf->ecx = get_ext_cpuid_leaf_1_ecx();
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei7_haswell_4770.cc
View File

@ -515,7 +515,7 @@ void corei7_haswell_4770_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [23:23] PerfCtrExtCore: core perf counter extensions support
// [24:24] PerfCtrExtNB: NB perf counter extensions support
// [31:25] Reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei7_icelake-u.cc
View File

@ -644,7 +644,7 @@ void corei7_icelake_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei7_ivy_bridge_3770K.cc
View File

@ -517,7 +517,7 @@ void corei7_ivy_bridge_3770k_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) con
// [23:23] PerfCtrExtCore: core perf counter extensions support
// [24:24] PerfCtrExtNB: NB perf counter extensions support
// [31:25] Reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel();
leaf->ecx = get_ext_cpuid_leaf_1_ecx();
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei7_sandy_bridge_2600K.cc
View File

@ -464,7 +464,7 @@ void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) c
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel();
leaf->ecx = get_ext_cpuid_leaf_1_ecx();
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/corei7_skylake-x.cc
View File

@ -591,7 +591,7 @@ void corei7_skylake_x_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280
// [28:28] PerfCtrExtL2I: L2I performance counter extensions support
// [31:29] Reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/sapphire_rapids.cc
View File

@ -760,7 +760,7 @@ void sapphire_rapids_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

2
bochs/cpu/cpudb/intel/tigerlake.cc
View File

@ -673,7 +673,7 @@ void tigerlake_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [31:14] reserved
leaf->ecx = get_ext_cpuid_leaf_1_ecx_intel(BX_CPUID_EXT1_ECX_PREFETCHW);
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// [10:0] Reserved for Intel

77
bochs/cpu/cpuid.cc
View File

@ -751,26 +751,26 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_1_edx(Bit32u extra) const
}
// Most of the bits in ECX are reserved for Intel
Bit32u bx_cpuid_t::get_ext_cpuid_leaf_1_ecx_intel(Bit32u extra) const
Bit32u bx_cpuid_t::get_ext_cpuid_leaf_1_ecx(Bit32u extra) const
{
Bit32u ecx = extra;
// * [0:0] LAHF/SAHF instructions support in 64-bit mode
// i [0:0] LAHF/SAHF instructions support in 64-bit mode
// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
// [2:2] SVM: Secure Virtual Machine (AMD)
// [3:3] Extended APIC Space
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
// * [5:5] LZCNT: LZCNT instruction support
// i [5:5] LZCNT: LZCNT instruction support
// [6:6] SSE4A: SSE4A Instructions support
// [7:7] Misaligned SSE support
// * [8:8] PREFETCHW: PREFETCHW instruction support - can be enabled through extra
// [9:9] OSVW: OS visible workarounds (AMD)
// [10:10] IBS: Instruction based sampling
// i [8:8] PREFETCHW: PREFETCHW instruction support - can be enabled through extra
// [9:9] OSVW: OS visible workarounds CPUID leaf (AMD)
// [10:10] IBS: Instruction based sampling (not supported in Bochs)
// [11:11] XOP: Extended Operations Support and XOP Prefix
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [12:12] SKINIT support (not supported in Bochs)
// [13:13] WDT: Watchdog timer support (not supported in Bochs)
// [14:14] Reserved
// [15:15] LWP: Light weight profiling
// [15:15] LWP: Light weight profiling (not supported in Bochs)
// [16:16] FMA4: Four-operand FMA instructions support
// [17:17] Reserved
// [18:18] Reserved
@ -784,16 +784,61 @@ Bit32u bx_cpuid_t::get_ext_cpuid_leaf_1_ecx_intel(Bit32u extra) const
// [26:26] Data breakpoint extension. Indicates support for MSR 0xC0011027 and MSRs 0xC001101[B:9]
// [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280
// [28:28] PerfCtrExtL2I: L2I performance counter extensions support
// [31:29] Reserved
// [29:29] MONITORX/MWAITX instructions support
// [30:30] AddrMaskExt: address mask extension support for instruction breakpoint
// [31:31] Reserved
#if BX_SUPPORT_X86_64
// [0:0] LAHF/SAHF instructions support in 64-bit mode
if (is_cpu_extension_supported(BX_ISA_LM_LAHF_SAHF))
ecx |= BX_CPUID_EXT1_ECX_LAHF_SAHF;
#endif
// [5:5] LZCNT: LZCNT instruction support
if (is_cpu_extension_supported(BX_ISA_LZCNT))
ecx |= BX_CPUID_EXT1_ECX_LZCNT;
// now AMD specific bits
#if BX_SUPPORT_SVM
// [2:2] SVM: Secure Virtual Machine (AMD)
if (is_cpu_extension_supported(BX_ISA_SVM))
ecx |= BX_CPUID_EXT1_ECX_SVM;
#endif
// [3:3] Extended APIC Space
if (is_cpu_extension_supported(BX_ISA_XAPIC_EXT))
ecx |= BX_CPUID_EXT1_ECX_EXT_APIC_SPACE;
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
if (is_cpu_extension_supported(BX_ISA_ALT_MOV_CR8))
ecx |= BX_CPUID_EXT1_ECX_ALT_MOV_CR8;
// [6:6] SSE4A: SSE4A Instructions support
if (is_cpu_extension_supported(BX_ISA_SSE4A))
ecx |= BX_CPUID_EXT1_ECX_SSE4A;
// [7:7] Misaligned SSE support
if (is_cpu_extension_supported(BX_ISA_MISALIGNED_SSE))
ecx |= BX_CPUID_EXT1_ECX_MISALIGNED_SSE;
// [11:11] XOP: Extended Operations Support and XOP Prefix
if (is_cpu_extension_supported(BX_ISA_XOP))
ecx |= BX_CPUID_EXT1_ECX_XOP;
// [16:16] FMA4: Four-operand FMA instructions support
if (is_cpu_extension_supported(BX_ISA_FMA4))
ecx |= BX_CPUID_EXT1_ECX_FMA4;
// [21:21] TBM: trailing bit manipulation instructions support
if (is_cpu_extension_supported(BX_ISA_TBM))
ecx |= BX_CPUID_EXT1_ECX_TBM;
#if BX_SUPPORT_MONITOR_MWAIT
// [29:29] MONITORX/MWAITX instructions support
if (is_cpu_extension_supported(BX_ISA_MONITORX_MWAITX))
ecx |= BX_CPUID_EXT1_ECX_MONITORX_MWAITX;
#endif
return ecx;
}
@ -1470,6 +1515,18 @@ void bx_cpuid_t::warning_messages(unsigned extension) const
void bx_cpuid_t::sanity_checks() const
{
if (is_cpu_extension_supported(BX_ISA_486) && ! is_cpu_extension_supported(BX_ISA_386))
BX_FATAL(("PANIC: 80386 ISA must be enabled for 80486 model !"));
if (is_cpu_extension_supported(BX_ISA_PENTIUM) && ! is_cpu_extension_supported(BX_ISA_486))
BX_FATAL(("PANIC: 80486 ISA must be enabled for Pentium model !"));
if (is_cpu_extension_supported(BX_ISA_P6) && ! is_cpu_extension_supported(BX_ISA_PENTIUM))
BX_FATAL(("PANIC: Pentium ISA must be enabled for P6 model !"));
if (is_cpu_extension_supported(BX_ISA_3DNOW) && ! is_cpu_extension_supported(BX_ISA_MMX))
BX_FATAL(("PANIC: 3dnow! ISA require MMX to be enabled !"));
if (is_cpu_extension_supported(BX_ISA_AVX10_VL512) && !is_cpu_extension_supported(BX_ISA_AVX10_1))
BX_FATAL(("PANIC: AVX10_VL512 is enabled when AVX10 is not supported !"));

2
bochs/cpu/cpuid.h
View File

@ -135,7 +135,7 @@ protected:
Bit32u get_std_cpuid_leaf_7_subleaf_1_eax(Bit32u extra = 0) const;
Bit32u get_std_cpuid_leaf_7_subleaf_1_edx(Bit32u extra = 0) const;
Bit32u get_ext_cpuid_leaf_1_ecx_intel(Bit32u extra = 0) const;
Bit32u get_ext_cpuid_leaf_1_ecx(Bit32u extra = 0) const;
Bit32u get_ext_cpuid_leaf_1_edx_amd(Bit32u extra = 0) const;
Bit32u get_ext_cpuid_leaf_1_edx_intel() const;

2
bochs/cpu/decoder/features.h
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@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023 The Bochs Project
// Copyright (C) 2023-2024 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public

62
bochs/cpu/generic_cpuid.cc
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@ -392,7 +392,7 @@ void bx_generic_cpuid_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
leaf->ebx = 0;
// ECX:
leaf->ecx = get_ext2_cpuid_features();
leaf->ecx = get_ext_cpuid_leaf_1_ecx(BX_CPUID_EXT1_ECX_PREFETCHW);
// EDX:
// Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD
@ -1007,66 +1007,6 @@ Bit32u bx_generic_cpuid_t::get_cpu_version_information(void) const
((model & 0x0f) << 4) | stepping;
}
#if BX_CPU_LEVEL >= 6
/* Get CPU feature flags. Returned by CPUID function 80000001 in ECX register */
Bit32u bx_generic_cpuid_t::get_ext2_cpuid_features(void) const
{
// ECX:
// [0:0] LAHF/SAHF instructions support in 64-bit mode
// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
// [2:2] SVM: Secure Virtual Machine (AMD)
// [3:3] Extended APIC Space
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
// [5:5] LZCNT: LZCNT instruction support
// [6:6] SSE4A: SSE4A Instructions support (deprecated?)
// [7:7] Misaligned SSE support
// [8:8] PREFETCHW: PREFETCHW instruction support
// [9:9] OSVW: OS visible workarounds (AMD)
// [10:10] IBS: Instruction based sampling
// [11:11] XOP: Extended Operations Support and XOP Prefix
// [12:12] SKINIT support
// [13:13] WDT: Watchdog timer support
// [14:14] reserved
// [15:15] LWP: Light weight profiling
// [16:16] FMA4: Four-operand FMA instructions support
// [18:17] reserved
// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
// [20:20] reserved
// [21:21] TBM: trailing bit manipulation instructions support
// [22:22] Topology extensions support
// [31:23] reserved
Bit32u features = 0;
#if BX_SUPPORT_X86_64
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_LONG_MODE))
features |= BX_CPUID_EXT1_ECX_LAHF_SAHF | BX_CPUID_EXT1_ECX_PREFETCHW;
#endif
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_MISALIGNED_SSE))
features |= BX_CPUID_EXT1_ECX_MISALIGNED_SSE;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_LZCNT))
features |= BX_CPUID_EXT1_ECX_LZCNT;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_SSE4A))
features |= BX_CPUID_EXT1_ECX_SSE4A;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_XOP))
features |= BX_CPUID_EXT1_ECX_XOP;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_FMA4))
features |= BX_CPUID_EXT1_ECX_FMA4;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_TBM))
features |= BX_CPUID_EXT1_ECX_TBM;
return features;
}
#endif
void bx_generic_cpuid_t::dump_cpuid(void) const
{
bx_cpuid_t::dump_cpuid(max_std_leaf, max_ext_leaf);

1
bochs/cpu/generic_cpuid.h
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@ -85,7 +85,6 @@ private:
void get_ext_cpuid_leaf_A(cpuid_function_t *leaf) const;
#endif
Bit32u get_ext2_cpuid_features(void) const;
#endif
Bit32u get_cpu_version_information(void) const;