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3416 Commits

Author SHA1 Message Date
Stanislav Shwartsman
045a1cd637 XSAVEC/XSAVES should be supported in SKL-X CPUID 2017-11-11 12:04:26 +00:00
Stanislav Shwartsman
180386cd74 VMOVSS/VMOVSD are VEX.VL ignore form and not VEX.L0 2017-11-11 11:58:07 +00:00
Stanislav Shwartsman
f89b8a2742 fixed opcode of ADOX instr 2017-11-11 10:42:21 +00:00
Stanislav Shwartsman
8261a91ce9 implemented GFNI instructions 2017-10-21 19:57:12 +00:00
Stanislav Shwartsman
b7f62a291c fixed compressed displ form for more avx512 instructions 2017-10-20 19:41:32 +00:00
Stanislav Shwartsman
da8d6e793f fixed compilation issues 2017-10-20 19:24:10 +00:00
Stanislav Shwartsman
bca076889b decode all the vbmi2 opcodes, fix vpcompress/vpexpand instruction handler names (affects disasm) 2017-10-20 18:50:10 +00:00
Stanislav Shwartsman
77a62a4dcd implemented (experimental, still untested) AVX512 VBMI2 extensions 2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
0afbb6cd3d fixed compilation when AVX is not configured in 2017-10-20 12:27:42 +00:00
Stanislav Shwartsman
5439647254 small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in 2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
ba1e5bbffa fixed accidentially broken XMM versions of AES instrructions 2017-10-19 20:25:05 +00:00
Stanislav Shwartsman
15ba88c195 implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ 2017-10-19 19:12:55 +00:00
Stanislav Shwartsman
ac442009aa lazy flags code small refactoring 2017-10-15 22:01:32 +00:00
Stanislav Shwartsman
6daa1ba9ba fixed compilation issue with EVEX enabled 2017-10-15 20:40:56 +00:00
Stanislav Shwartsman
944f37b1f2 implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions 2017-10-15 20:33:19 +00:00
Stanislav Shwartsman
0d190eec8e implemented AVX-512 VNNI instructions 2017-10-15 19:17:07 +00:00
Stanislav Shwartsman
4179e6f939 add some const 2017-10-14 18:42:12 +00:00
Stanislav Shwartsman
69f27439db added new cpuid flags mentioned in new Intel SDM future extensions rev030 doc 2017-10-13 20:27:52 +00:00
Stanislav Shwartsman
2d3d62db5f cleaned cr2 print in 32-bit mode 2017-08-22 21:14:39 +00:00
Stanislav Shwartsman
2a55ba0a39 Merge set of debugger improvements by Doug Gale <doug16k> 
Here is his original comment:

I have made several improvements in the debugger.
I have fixed several issues with proper handling of 64-bit addresses, and added support for 64 bit symbols.
I also have added several symbol lookups.
 2017-08-22 21:03:58 +00:00
Stanislav Shwartsman
f490b00beb added support for conditional breakpoints in Bochs debugger 2017-08-22 18:47:18 +00:00
Stanislav Shwartsman
7f4a9b4b08 skylake CPUID should compile also with no EVEX 2017-08-09 21:04:15 +00:00
Stanislav Shwartsman
7f01a7d9b6 remove obsolete comment 2017-08-09 20:37:43 +00:00
Stanislav Shwartsman
b2fdbd1274 added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 20:36:17 +00:00
Stanislav Shwartsman
54e969b749 disasm update 2017-06-05 21:05:47 +00:00
Stanislav Shwartsman
20e9e33662 internal disasm updates 2017-06-05 20:49:04 +00:00
Stanislav Shwartsman
3f4f18de7a internal disasm updates 2017-06-05 20:28:33 +00:00
Stanislav Shwartsman
46ef85ce0f avoid using magic constants for disasm source metadata 2017-06-05 19:55:40 +00:00
Stanislav Shwartsman
555bb8f8b6 updates to prev commit 2017-06-01 08:41:41 +00:00
Stanislav Shwartsman
6ab4fd597b implement another form of AR field packing used in SKL, in addition on present NHM format 2017-06-01 08:31:20 +00:00
Stanislav Shwartsman
bde8a1f69d fixed ifdef typo 2017-06-01 07:48:54 +00:00
Stanislav Shwartsman
22e9051716 implemented correct VM-exit instruction information for INVPCID, RDRAND/RDSEED and XSAVES/XRSTORS instruction Vmexits 2017-05-31 13:16:49 +00:00
Stanislav Shwartsman
bb43ac527b fixed decoder issue when decoding opcode 8f (aka xop prefix) as well 2017-05-27 10:32:44 +00:00
Stanislav Shwartsman
54c109ceb4 VEX and EVEX opcodes should be considered as 2-byte opcode, always attempt to fetch 2nd byte even if #UD is already detected 2017-05-26 11:46:02 +00:00
Stanislav Shwartsman
af76e0c412 fixes for debugger and disasm 2017-05-10 18:31:59 +00:00
Stanislav Shwartsman
1ca366609f add memsize for non-evex memory refrences in disasm 2017-05-09 19:49:27 +00:00
Stanislav Shwartsman
f8abddafcf bugfix in disasm 2017-05-09 19:34:03 +00:00
Stanislav Shwartsman
1d48973c80 updates in fetchdecode.h to help automatic disasm to determined memaccess size 2017-05-09 12:06:02 +00:00
Stanislav Shwartsman
e357da9150 update (c) for fpu files 2017-05-05 21:09:27 +00:00
Stanislav Shwartsman
1abfcd39ff implement FOPCODE and FDP deprecation CPU features 2017-05-05 20:56:13 +00:00
Stanislav Shwartsman
fce7476bda convert magic defines into static const variables 2017-05-03 18:20:13 +00:00
Stanislav Shwartsman
3d51439090 fixed compilation err for CPU_LEVEL=5 2017-04-13 05:33:29 +00:00
Stanislav Shwartsman
1a3ff4b438 fixed bogus error message 2017-04-11 18:35:17 +00:00
Stanislav Shwartsman
bad84e48cd remove redundant memory access from IRET 2017-04-01 05:49:01 +00:00
Stanislav Shwartsman
e351aaa28a update (c) for tlb.h 2017-03-31 07:34:44 +00:00
Stanislav Shwartsman
a51eb1cc39 added more debug info for TLB through param tree, update year in the (c) 2017-03-31 07:34:08 +00:00
Stanislav Shwartsman
c9c3672509 allow monitor to UC memory type but not MONITORX 2017-03-31 07:00:36 +00:00
Stanislav Shwartsman
566a7aa82b fixed softfloat FUZ condition. fixed/optimized pmaddwd computing function 2017-03-30 22:11:38 +00:00
Stanislav Shwartsman
a6e7ffb284 implemented undefined flags behavior for SHRD instruction matching HW 2017-03-30 22:03:38 +00:00
Stanislav Shwartsman
097310cd00 fixed integer overflow while computing shift flags, avoid using bx_bool while working with flags for more robust code 2017-03-30 21:53:39 +00:00
Stanislav Shwartsman
862e817884 fixed typo caused compilation err 2017-03-28 19:13:20 +00:00
Stanislav Shwartsman
31d29734d6 some comments about more CPUID leaf 80000008.EBX by Ryzen 2017-03-28 19:11:42 +00:00
Stanislav Shwartsman
b7b0165d3c new naming convention for UD opcodes 2017-03-28 19:00:00 +00:00
Stanislav Shwartsman
a673612784 fixed permission checks performed by CLFLUSH/CLFLUSHOPT/MONITOR* instructions 2017-03-28 18:52:53 +00:00
Stanislav Shwartsman
e5c64b3b56 cleanup of warning messages from cpuid code 2017-03-26 20:12:14 +00:00
Stanislav Shwartsman
2b79061127 Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model 2017-03-26 19:14:15 +00:00
Volker Ruppert
dd2d03ec0a The 'del' command doesn't like forward slashes, so the MSVC nmake 'clean' 
target skipped files in subfolders. Updated cpu makefile dependencies.
 2017-03-26 15:55:57 +00:00
Stanislav Shwartsman
411ea954b4 implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 20:12:31 +00:00
Volker Ruppert
9bef555f3e Updated build test script and fixed compilation without FPU. 2017-03-19 09:50:16 +00:00
Volker Ruppert
640f5e2ce9 Fixed compilation error. 2017-03-19 07:26:56 +00:00
Stanislav Shwartsman
2c5588cda0 convert some defines to enums and consts 2017-03-18 21:25:06 +00:00
Stanislav Shwartsman
2809e7f5ad fixed warnings in the cpu code 2017-03-18 07:32:17 +00:00
Stanislav Shwartsman
15d9b068a3 fix msvc warnings 2017-03-17 17:35:15 +00:00
Stanislav Shwartsman
99bfbdf139 add xss exiting bitmap to save/restore 2017-03-16 20:23:49 +00:00
Stanislav Shwartsman
3f80447a10 fixed compilation err with x86-64 disabled 2017-03-16 20:13:42 +00:00
Stanislav Shwartsman
be4c6c7ae5 SMAP opcodes are No-SSE-Prefix 2017-03-16 16:20:58 +00:00
Stanislav Shwartsman
172b0106ac imvent a bochs feature for AMD TCE and enable EFER.TCE bit 2017-03-15 22:52:08 +00:00
Stanislav Shwartsman
6edf22e754 finally figured out what TCE means in AMD CPUID - and it has EFER.TCE bit related to it 2017-03-15 22:48:27 +00:00
Stanislav Shwartsman
ebbf8f9e0f adjustments in AMD Ryzen CPUID 2017-03-15 22:14:10 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Volker Ruppert
8796abeea6 Some fixes in the build system. 
- Makefile: cleanup of the 'clean' target (adds missing 'bxhub').
- configure script: create cpudb subdirectories if necessary for building
  outside of the source tree.
- cpudb Makefile: clean object files from new location.
 2017-03-15 16:51:32 +00:00
Stanislav Shwartsman
c0701a6d42 fixup for Ryzen cpuid 2017-03-13 20:23:39 +00:00
Stanislav Shwartsman
402e2cfad0 move cpuid warning messages to base cpuid class - reduce code cleanup 2017-03-13 19:59:48 +00:00
Stanislav Shwartsman
07166f14b7 reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct) 2017-03-13 19:44:14 +00:00
Stanislav Shwartsman
980eaa7937 move cpuid leaf 80000008 to base bx_cpuid_t class to remove code dupolication 2017-03-09 21:25:18 +00:00
Stanislav Shwartsman
8664f8f21e add vex.w into bxInstruction to be used in disasm 2017-01-28 19:25:30 +00:00
Stanislav Shwartsman
49c537521a simplify disasm code by splitting it into functions 2017-01-22 19:53:42 +00:00
Volker Ruppert
6cf6f6967a Fixed cpu "make clean" target. 2017-01-13 16:13:42 +00:00
Stanislav Shwartsman
af1d83f35d update (c) 2017-01-11 20:54:09 +00:00
Stanislav Shwartsman
521d2d10c4 correctly fixed x32 emu compilation err + bugfix for AVX decoder 2017-01-11 20:51:58 +00:00
Stanislav Shwartsman
72e5213ff4 compilation fix and code simplifcation 2017-01-11 19:12:06 +00:00
Stanislav Shwartsman
90c4cb31c5 add SVN header to newly added files 2017-01-10 20:16:24 +00:00
Stanislav Shwartsman
10eb193e01 step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together 2017-01-10 20:15:17 +00:00
Stanislav Shwartsman
9bd99a604f implemented recently announced AVX-512 extension VPOPCNT 2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
e613e9ff86 fixed compilation err when no AVX is enabled 2016-12-12 06:18:57 +00:00
Stanislav Shwartsman
7b2a8bb340 added missing EPT misconfig condition check 2016-12-10 05:06:59 +00:00
Stanislav Shwartsman
46b4a76cd3 fetchdecode rework step 0.1, no impact on correctness, small speedup 2016-12-09 12:34:37 +00:00
Stanislav Shwartsman
bd24d7fb17 fixed reset value of xcr0 as published in latest Intel SDM update 2016-10-08 15:17:12 +00:00
Stanislav Shwartsman
1543034fb7 in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore 2016-10-02 11:56:18 +00:00
Stanislav Shwartsman
239f793f37 in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore 2016-10-02 11:54:19 +00:00
Stanislav Shwartsman
42b0714992 rename fetchdecode.cc -> fetchdecode32.cc 2016-09-25 18:25:47 +00:00
Stanislav Shwartsman
d9e818cd5d refactoring in the Bochs decoder code 2016-09-25 18:19:59 +00:00
Stanislav Shwartsman
8f20cecbae fixed code style in fetchdecode.cc, avoid code duplication 2016-09-08 17:29:09 +00:00
Stanislav Shwartsman
b7091b09f6 cleanup in fetchdecode functions 2016-09-08 15:09:29 +00:00
Stanislav Shwartsman
14b7fff442 remove unexpected change in fetchdecode.cc 2016-08-30 18:43:36 +00:00
Stanislav Shwartsman
032da78e52 remove SMP and AVX from Android build script. reduce the binary size and make faster binary (SMP makes binary a lot slower) 2016-08-30 18:42:39 +00:00
Volker Ruppert
cd68194269 Added Android host platform support to Bochs based on SF patch #534. 
- added Android case to the configure script.
- renamed file memory.h to memory-bochs.h to fix conflict with NDK.
- fixed Android issues in some files.
 2016-08-12 17:06:14 +00:00
Stanislav Shwartsman
46e932d04e fixed INIT cpu state according to clarification published in SDM rev059 2016-07-17 19:16:58 +00:00
Stanislav Shwartsman
88637aa9ef fixed potential uninitialized variable access when decoding AVX/XOP/EVEX 2016-07-06 09:09:49 +00:00
Stanislav Shwartsman
6761495f7e second step if Bochs decoder refactoring: extracted assign_srcs code to separate methods 2016-07-05 20:42:25 +00:00