Stanislav Shwartsman
9bd99a604f
implemented recently announced AVX-512 extension VPOPCNT
2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
239f793f37
in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore
2016-10-02 11:54:19 +00:00
Stanislav Shwartsman
793ceb0d8c
fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header
2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
adc143684b
implemented Intel architecture extensions published in recently published SDM 058:
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! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction
Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
bcb36e81fa
experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys
2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
88be61c3d9
add new cpuid bit announced in sdm rev057
2015-12-29 20:21:08 +00:00
Stanislav Shwartsman
8d13b61319
implemented TSC Scaling VMX feature according to timestamp-counter for virtualization whitepaper published by Intel
2015-09-30 18:44:01 +00:00
Stanislav Shwartsman
be4b73c6d2
extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class
2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
9315742f3d
cleanups of vmcs mapping related stuff
2015-07-07 21:06:56 +00:00
Stanislav Shwartsman
5fe1423ab6
introducr new class for VMCS mapping so it can be customized per cpuid
2015-07-06 18:46:57 +00:00
Stanislav Shwartsman
bc25883087
add new definitions from most recent AMD Software Developers Manual update. TODO: implement new AMD's MONITORX/MWAITX extensions
2015-06-22 21:46:50 +00:00
Stanislav Shwartsman
2185d21eb7
fixed comments for PML acronym
2015-05-05 19:52:05 +00:00
Stanislav Shwartsman
16ab385e1d
added cpuid/creg bits definition announced in recent 054 update of Intel SDM
2015-05-05 19:28:25 +00:00
Stanislav Shwartsman
080ceb8293
don't crash when running on 386 with no FPU model
2015-03-27 21:39:24 +00:00
Stanislav Shwartsman
901b7be1a8
code reorg
2015-02-12 20:18:35 +00:00
Stanislav Shwartsman
b60d7d3154
Cleanup of CPUDB modules, moved common functionality into bx_cpuid_t base class
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Added Pentium (P54C) AKA Pentium with no MMX to CPUDB
2015-02-11 21:31:17 +00:00
Stanislav Shwartsman
03dab0b0c9
remove debug prints from param tree dump in xml format, small code reorg
2014-11-30 21:26:33 +00:00
Stanislav Shwartsman
987e2ad223
Added definitions from recently published Intel Architecture
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Instruction Set Extensions Programming Reference rev22.
Implemented CLWB instruction
2014-11-01 13:12:24 +00:00
Stanislav Shwartsman
5f4e7f8b49
fixed compilation when APIC if snot enabled
2014-11-01 10:25:42 +00:00
Stanislav Shwartsman
618bc234ab
changes in comments
2014-10-24 11:18:52 +00:00
Stanislav Shwartsman
caab07e580
move common code (extended topology leaf) into base cpuid class to save code duplication
2014-10-15 14:25:08 +00:00
Stanislav Shwartsman
f8267ec3a7
rework in CPUID code (fixed code duplication). Re-enable perfmon reporting in CPUID because Win8/Win10 installation doesn't want to start without perfmon reported. TODO: implement basic perfmon support (at least only fixed counters) because win7-64 doesn't install with perfmon reported but not implemented
2014-10-15 08:04:38 +00:00
Stanislav Shwartsman
e2e6f5a62b
Update CPUID defines after recently published
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Intel Architecture Instruction Set Extensions Programming Reference rev-021
Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied
implemented AVX512_IFMA532 instructions
implemented AVX512_VBMI instructions
still missing: VPMULTISHIFTQB - VBMI instruction (coming soon)
2014-09-26 12:14:53 +00:00
Stanislav Shwartsman
b6147d9de8
fixed debugger enabled code
2014-08-31 18:48:04 +00:00
Stanislav Shwartsman
9f57e70d5f
Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions
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Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
94864fb9bc
Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20.
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https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf
Most of the instructions are implemented, more on the way.
+ few bugfixes for legacy AVX-512 emulation
AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
2014-07-18 11:14:25 +00:00
Stanislav Shwartsman
d19727d75b
updated AMD feature names in cpuid.h (taken from latest AMD software dev manuals)
2014-05-05 20:11:14 +00:00
Stanislav Shwartsman
378e7e16eb
fixed major code duplication in CPUDB classes
2014-03-15 19:24:42 +00:00
Stanislav Shwartsman
aea9ae1976
added definitions (CPUID bit, VMX fields and VMXEXIT reasons, etc) from recently published Intel SDM rev049
2014-02-06 17:05:20 +00:00
Stanislav Shwartsman
36ba25847f
Implemented last missed AVX-512 unsigned convert instructions
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The only missed AVX-512 opcodes now are:
512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH
512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0 25 VPMOVSXDQ
512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0 35 VPMOVSzDQ
512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD
512.66.0F38.W0 4C VRCP14PS
512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
NDS.LIG.66.0F38.W1 4F VRSQRT14SD
NDS.512.66.0F3A.W0 03 VALIGND
NDS.512.66.0F3A.W1 03 VALIGNQ
512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD
512.66.0F3A.W0 19 VEXTRACTF32x4
512.66.0F3A.W1 1B VEXTRACTF64x4
512.66.0F3A.W0 39 VEXTRACTI32x4
512.66.0F3A.W1 3B VEXTRACTI64x4
512.66.0F3A.W0 26 VGETMANTPS
512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
NDS.LIG.66.0F3A.W1 27 VGETMANTSD
2014-01-28 12:57:38 +00:00
Stanislav Shwartsman
e1012f1165
add vmcs revision id interface to CPUID class
2013-10-14 18:35:56 +00:00
Stanislav Shwartsman
7297323c69
First step of AVX512 support implementation (simplest)
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decode and implement KMASK manipulation instructions
disasm: coming soon
2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
852b5c3749
implemented SHA new instructions announced in recent Intel SDM extensions document rev015
2013-07-24 18:44:22 +00:00
Stanislav Shwartsman
fd71b03353
add some definitions introduced in recent Intel SDM extensions document (rev015)
2013-07-23 20:51:52 +00:00
Stanislav Shwartsman
c7698a5589
implemented fcs/fds deprecation. added haswell to cpudb.h as well
2013-06-20 20:12:53 +00:00
Stanislav Shwartsman
9651b5d53c
bugfix: vmx preemption timer vmexit should not wakeup CPU from sleep state. cpuid: added definitions from recently published intel SDM rev047
2013-06-04 20:28:27 +00:00
Stanislav Shwartsman
2bca9b8273
updates in CPUID defines after new published AMD SDM
2013-05-17 19:41:57 +00:00
Stanislav Shwartsman
9b958b3a05
allow to select CPU level = 5 from .bochsrc even when Bochs is compiled with CPU_LEVEL=6
2013-04-17 19:46:11 +00:00
Stanislav Shwartsman
64df073617
implemented virtualization exception feature
2013-01-28 16:30:25 +00:00
Stanislav Shwartsman
4bed791ccb
Added year 2013 to Copyright in all files already modified in new year
2013-01-19 20:45:03 +00:00
Stanislav Shwartsman
c337b7babb
Intel Software Developers Manual rev45 was released
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Added CPUID bits and preparations for newly documented VMX features
2013-01-16 16:57:48 +00:00
Stanislav Shwartsman
64f9c12bbc
name new CPUID bits from AMD
2012-11-10 11:00:09 +00:00
Stanislav Shwartsman
744001e35e
Implemented VMX APIC Registers Virtualization and VMX Virtual Interrupt Delivery emulation
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Bugfix: VMX: VmEntry should do TPR Virtualization (TPR Shadow + APIC Access Virtualization case is affected) and even could possibly cause TPR Threshold VMEXIT
2012-10-26 18:43:53 +00:00
Stanislav Shwartsman
dbb23aed43
close another SMC hole
2012-10-01 18:19:09 +00:00
Stanislav Shwartsman
2f3c7ff8e4
implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14
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fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc
Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
f1fd44b2cf
preparations for apic regs virtualization feature described in SDM rev044
2012-09-06 15:21:08 +00:00
Stanislav Shwartsman
5d66e8450e
implemented ADCX/ADOX instructions from rev013 of arch extensions published by Intel
2012-07-12 14:51:54 +00:00
Stanislav Shwartsman
bafde35c9c
Intel Architecture
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Instruction Set Extensions
Programming Reference
rev013
was published including RDSEED and ADCX/ADOX instructions
add CPUID bits and VMX controls mentioned in the document
2012-07-11 18:58:00 +00:00
Stanislav Shwartsman
39c14ef0d1
Implemented EPT A/D extensions support.
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Bochs is fully aligned with the latest published revision of
Intel Architecture Manual (revision 043) now.
2012-05-02 18:11:39 +00:00
Stanislav Shwartsman
bb7a648d91
Major commit !
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------------
Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.
! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.
Some CPUID modules rework done to enable Toliman configuration.
Ckean up 'executable' attribute from all CPU source files.
2012-02-13 23:29:01 +00:00
