36ba25847f
The only missed AVX-512 opcodes now are: 512.66.0F38.W0 13 VCVTPH2PS 512.66.0F3A.W0 1D VCVTPS2PH 512.66.0F38.WIG 21 VPMOVSXBD 512.66.0F38.WIG 22 VPMOVSXBQ 512.66.0F38.WIG 23 VPMOVSXWD 512.66.0F38.WIG 24 VPMOVSXWQ 512.66.0F38.W0 25 VPMOVSXDQ 512.66.0F38.WIG 31 VPMOVSZBD 512.66.0F38.WIG 32 VPMOVSZBQ 512.66.0F38.WIG 33 VPMOVSZWD 512.66.0F38.WIG 34 VPMOVSZWQ 512.66.0F38.W0 35 VPMOVSzDQ 512.66.0F38.W0 2C VSCALEFPS 512.66.0F38.W1 2C VSCALEFPD NDS.LIG.66.0F38.W0 2D VSCALESS NDS.LIG.66.0F38.W1 2D VSCALESD 512.66.0F38.W0 4C VRCP14PS 512.66.0F38.W1 4C VRCP14PD NDS.LIG.66.0F38.W0 4D VRCP14SS NDS.LIG.66.0F38.W1 4D VRCP14SD 512.66.0F38.W0 4E VRSQRT14PS 512.66.0F38.W1 4E VRSQRT14PD NDS.LIG.66.0F38.W0 4F VRSQRT14SS NDS.LIG.66.0F38.W1 4F VRSQRT14SD NDS.512.66.0F3A.W0 03 VALIGND NDS.512.66.0F3A.W1 03 VALIGNQ 512.66.0F3A.W0 08 VRNDSCALEPS 512.66.0F3A.W1 09 VRNDSCALEPD NDS.LIG.66.0F3A.W1 0A VRNDSCALESS NDS.LIG.66.0F3A.W1 0B VRNDSCALESD 512.66.0F3A.W0 19 VEXTRACTF32x4 512.66.0F3A.W1 1B VEXTRACTF64x4 512.66.0F3A.W0 39 VEXTRACTI32x4 512.66.0F3A.W1 3B VEXTRACTI64x4 512.66.0F3A.W0 26 VGETMANTPS 512.66.0F3A.W1 26 VGETMANTPD NDS.LIG.66.0F3A.W0 27 VGETMANTSS NDS.LIG.66.0F3A.W1 27 VGETMANTSD
500 lines
24 KiB
C++
500 lines
24 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2010-2014 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_CPU_MODEL_SPECIFIC
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#define BX_CPU_MODEL_SPECIFIC
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struct cpuid_function_t {
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Bit32u eax;
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Bit32u ebx;
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Bit32u ecx;
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Bit32u edx;
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};
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class bx_cpuid_t {
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public:
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bx_cpuid_t(BX_CPU_C *_cpu);
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virtual ~bx_cpuid_t() {}
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// return CPU name
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virtual const char *get_name(void) const { return NULL; }
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virtual Bit64u get_isa_extensions_bitmask(void) const = 0;
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virtual Bit32u get_cpu_extensions_bitmask(void) const = 0;
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#if BX_SUPPORT_VMX
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virtual Bit32u get_vmx_extensions_bitmask(void) const { return 0; }
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#endif
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#if BX_SUPPORT_SVM
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virtual Bit32u get_svm_extensions_bitmask(void) const { return 0; }
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#endif
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virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const = 0;
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virtual void dump_cpuid(void) const = 0;
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#if BX_CPU_LEVEL >= 5
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virtual int rdmsr(Bit32u index, Bit64u *msr) { return -1; }
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virtual int wrmsr(Bit32u index, Bit64u msr) { return -1; }
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#endif
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#define BX_VMX_VMCS_REVISION_ID 0x2B /* better to be unique bochs VMCS revision id */
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#if BX_SUPPORT_VMX
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virtual Bit32u get_vmcs_revision_id(void) const { return BX_VMX_VMCS_REVISION_ID; }
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#endif
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protected:
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BX_CPU_C *cpu;
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unsigned nprocessors;
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unsigned ncores;
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unsigned nthreads;
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void get_reserved_leaf(cpuid_function_t *leaf) const
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{
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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};
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typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
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// cpuid ISA (duplicated in disasm.h)
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#define BX_ISA_X87 (BX_CONST64(1) << 0) /* FPU (X87) instruction */
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#define BX_ISA_486 (BX_CONST64(1) << 1) /* 486 new instruction */
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#define BX_ISA_PENTIUM (BX_CONST64(1) << 2) /* Pentium new instruction */
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#define BX_ISA_P6 (BX_CONST64(1) << 3) /* P6 new instruction */
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#define BX_ISA_MMX (BX_CONST64(1) << 4) /* MMX instruction */
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#define BX_ISA_3DNOW (BX_CONST64(1) << 5) /* 3DNow! instruction (AMD) */
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#define BX_ISA_SYSCALL_SYSRET_LEGACY (BX_CONST64(1) << 6) /* SYSCALL/SYSRET in legacy mode (AMD) */
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#define BX_ISA_SYSENTER_SYSEXIT (BX_CONST64(1) << 7) /* SYSENTER/SYSEXIT instruction */
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#define BX_ISA_CLFLUSH (BX_CONST64(1) << 8) /* CLFLUSH instruction */
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#define BX_ISA_SSE (BX_CONST64(1) << 9) /* SSE instruction */
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#define BX_ISA_SSE2 (BX_CONST64(1) << 10) /* SSE2 instruction */
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#define BX_ISA_SSE3 (BX_CONST64(1) << 11) /* SSE3 instruction */
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#define BX_ISA_SSSE3 (BX_CONST64(1) << 12) /* SSSE3 instruction */
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#define BX_ISA_SSE4_1 (BX_CONST64(1) << 13) /* SSE4_1 instruction */
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#define BX_ISA_SSE4_2 (BX_CONST64(1) << 14) /* SSE4_2 instruction */
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#define BX_ISA_POPCNT (BX_CONST64(1) << 15) /* POPCNT instruction */
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#define BX_ISA_MONITOR_MWAIT (BX_CONST64(1) << 16) /* MONITOR/MWAIT instruction */
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#define BX_ISA_VMX (BX_CONST64(1) << 17) /* VMX instruction */
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#define BX_ISA_SMX (BX_CONST64(1) << 18) /* SMX instruction */
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#define BX_ISA_LM_LAHF_SAHF (BX_CONST64(1) << 19) /* Long Mode LAHF/SAHF instruction */
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#define BX_ISA_CMPXCHG16B (BX_CONST64(1) << 20) /* CMPXCHG16B instruction */
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#define BX_ISA_RDTSCP (BX_CONST64(1) << 21) /* RDTSCP instruction */
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#define BX_ISA_XSAVE (BX_CONST64(1) << 22) /* XSAVE/XRSTOR extensions instruction */
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#define BX_ISA_XSAVEOPT (BX_CONST64(1) << 23) /* XSAVEOPT instruction */
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#define BX_ISA_AES_PCLMULQDQ (BX_CONST64(1) << 24) /* AES+PCLMULQDQ instruction */
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#define BX_ISA_MOVBE (BX_CONST64(1) << 25) /* MOVBE Intel Atom(R) instruction */
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#define BX_ISA_FSGSBASE (BX_CONST64(1) << 26) /* FS/GS BASE access instruction */
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#define BX_ISA_INVPCID (BX_CONST64(1) << 27) /* INVPCID instruction */
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#define BX_ISA_AVX (BX_CONST64(1) << 28) /* AVX instruction */
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#define BX_ISA_AVX2 (BX_CONST64(1) << 29) /* AVX2 instruction */
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#define BX_ISA_AVX_F16C (BX_CONST64(1) << 30) /* AVX F16 convert instruction */
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#define BX_ISA_AVX_FMA (BX_CONST64(1) << 31) /* AVX FMA instruction */
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#define BX_ISA_SSE4A (BX_CONST64(1) << 32) /* SSE4A instruction (AMD) */
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#define BX_ISA_LZCNT (BX_CONST64(1) << 33) /* LZCNT instruction */
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#define BX_ISA_BMI1 (BX_CONST64(1) << 34) /* BMI1 instruction */
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#define BX_ISA_BMI2 (BX_CONST64(1) << 35) /* BMI2 instruction */
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#define BX_ISA_FMA4 (BX_CONST64(1) << 36) /* FMA4 instruction (AMD) */
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#define BX_ISA_XOP (BX_CONST64(1) << 37) /* XOP instruction (AMD) */
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#define BX_ISA_TBM (BX_CONST64(1) << 38) /* TBM instruction (AMD) */
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#define BX_ISA_SVM (BX_CONST64(1) << 39) /* SVM instruction (AMD) */
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#define BX_ISA_RDRAND (BX_CONST64(1) << 40) /* RDRAND instruction */
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#define BX_ISA_ADX (BX_CONST64(1) << 41) /* ADCX/ADOX instruction */
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#define BX_ISA_SMAP (BX_CONST64(1) << 42) /* SMAP support */
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#define BX_ISA_RDSEED (BX_CONST64(1) << 43) /* RDSEED instruction */
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#define BX_ISA_SHA (BX_CONST64(1) << 44) /* SHA instruction */
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#define BX_ISA_AVX512 (BX_CONST64(1) << 45) /* AVX-512 instruction */
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#define BX_ISA_AVX512_CD (BX_CONST64(1) << 46) /* AVX-512 Conflict Detection instruction */
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#define BX_ISA_AVX512_PF (BX_CONST64(1) << 47) /* AVX-512 Sparse Prefetch instruction */
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#define BX_ISA_AVX512_ER (BX_CONST64(1) << 48) /* AVX-512 Exponential/Reciprocal instruction */
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// cpuid non-ISA features
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#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */
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#define BX_CPU_VME (1 << 1) /* VME support */
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#define BX_CPU_PSE (1 << 2) /* PSE support */
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#define BX_CPU_PAE (1 << 3) /* PAE support */
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#define BX_CPU_PGE (1 << 4) /* Global Pages support */
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#define BX_CPU_PSE36 (1 << 5) /* PSE-36 support */
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#define BX_CPU_MTRR (1 << 6) /* MTRR support */
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#define BX_CPU_PAT (1 << 7) /* PAT support */
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#define BX_CPU_XAPIC (1 << 8) /* XAPIC support */
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#define BX_CPU_X2APIC (1 << 9) /* X2APIC support */
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#define BX_CPU_XAPIC_EXT (1 << 10) /* XAPIC Extensions support */
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#define BX_CPU_NX (1 << 11) /* No-Execute support */
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#define BX_CPU_LONG_MODE (1 << 12) /* Long Mode (x86-64) support */
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#define BX_CPU_1G_PAGES (1 << 13) /* 1Gb pages support */
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#define BX_CPU_PCID (1 << 14) /* PCID pages support */
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#define BX_CPU_SMEP (1 << 15) /* SMEP support */
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#define BX_CPU_FFXSR (1 << 16) /* EFER.FFXSR support */
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#define BX_CPU_ALT_MOV_CR8 (1 << 17) /* LOCK CR0 access CR8 */
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#define BX_CPU_TSC_DEADLINE (1 << 18) /* TSC-Deadline */
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#define BX_CPU_MISALIGNED_SSE (1 << 19) /* Misaligned SSE */
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#define BX_CPU_FCS_FDS_DEPRECATION (1 << 20) /* FCS/FDS Deprecation */
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// cpuid VMX features
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#define BX_VMX_TPR_SHADOW (1 << 0) /* TPR shadow */
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#define BX_VMX_VIRTUAL_NMI (1 << 1) /* Virtual NMI */
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#define BX_VMX_APIC_VIRTUALIZATION (1 << 2) /* APIC Access Virtualization */
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#define BX_VMX_WBINVD_VMEXIT (1 << 3) /* WBINVD VMEXIT */
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#define BX_VMX_PERF_GLOBAL_CTRL (1 << 4) /* Save/Restore MSR_PERF_GLOBAL_CTRL */
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#define BX_VMX_MONITOR_TRAP_FLAG (1 << 5) /* Monitor trap Flag (MTF) */
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#define BX_VMX_X2APIC_VIRTUALIZATION (1 << 6) /* Virtualize X2APIC */
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#define BX_VMX_EPT (1 << 7) /* Extended Page Tables (EPT) */
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#define BX_VMX_VPID (1 << 8) /* VPID */
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#define BX_VMX_UNRESTRICTED_GUEST (1 << 9) /* Unrestricted Guest */
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#define BX_VMX_PREEMPTION_TIMER (1 << 10) /* VMX preemption timer */
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#define BX_VMX_SAVE_DEBUGCTL_DISABLE (1 << 11) /* Disable Save/Restore of MSR_DEBUGCTL */
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#define BX_VMX_PAT (1 << 12) /* Save/Restore MSR_PAT */
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#define BX_VMX_EFER (1 << 13) /* Save/Restore MSR_EFER */
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#define BX_VMX_DESCRIPTOR_TABLE_EXIT (1 << 14) /* Descriptor Table VMEXIT */
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#define BX_VMX_PAUSE_LOOP_EXITING (1 << 15) /* Pause Loop Exiting */
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#define BX_VMX_EPTP_SWITCHING (1 << 16) /* EPTP switching (VM Function 0) */
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#define BX_VMX_EPT_ACCESS_DIRTY (1 << 17) /* Extended Page Tables (EPT) A/D Bits */
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#define BX_VMX_VINTR_DELIVERY (1 << 18) /* Virtual Interrupt Delivery */
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#define BX_VMX_POSTED_INSTERRUPTS (1 << 19) /* Posted Interrupts support - not implemented yet */
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#define BX_VMX_VMCS_SHADOWING (1 << 20) /* VMCS Shadowing */
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#define BX_VMX_EPT_EXCEPTION (1 << 21) /* EPT Violation (#VE) exception */
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// CPUID defines - STD features CPUID[0x00000001].EDX
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// ----------------------------
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// [0:0] FPU on chip
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// [1:1] VME: Virtual-8086 Mode enhancements
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// [2:2] DE: Debug Extensions (I/O breakpoints)
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// [3:3] PSE: Page Size Extensions
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// [4:4] TSC: Time Stamp Counter
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// [5:5] MSR: RDMSR and WRMSR support
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// [6:6] PAE: Physical Address Extensions
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// [7:7] MCE: Machine Check Exception
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// [8:8] CXS: CMPXCHG8B instruction
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// [9:9] APIC: APIC on Chip
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// [10:10] Reserved
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// [11:11] SYSENTER/SYSEXIT support
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// [12:12] MTRR: Memory Type Range Reg
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// [13:13] PGE/PTE Global Bit
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// [14:14] MCA: Machine Check Architecture
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// [15:15] CMOV: Cond Mov/Cmp Instructions
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// [16:16] PAT: Page Attribute Table
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// [17:17] PSE-36: Physical Address Extensions
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// [18:18] PSN: Processor Serial Number
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// [19:19] CLFLUSH: CLFLUSH Instruction support
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// [20:20] Reserved
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// [21:21] DS: Debug Store
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// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
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// [23:23] MMX Technology
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// [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
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// [25:25] SSE: SSE Extensions
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// [26:26] SSE2: SSE2 Extensions
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// [27:27] Self Snoop
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// [28:28] Hyper Threading Technology
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// [29:29] TM: Thermal Monitor
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// [30:30] Reserved
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// [31:31] PBE: Pending Break Enable
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#define BX_CPUID_STD_X87 (1 << 0)
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#define BX_CPUID_STD_VME (1 << 1)
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#define BX_CPUID_STD_DEBUG_EXTENSIONS (1 << 2)
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#define BX_CPUID_STD_PSE (1 << 3)
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#define BX_CPUID_STD_TSC (1 << 4)
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#define BX_CPUID_STD_MSR (1 << 5)
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#define BX_CPUID_STD_PAE (1 << 6)
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#define BX_CPUID_STD_MCE (1 << 7)
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#define BX_CPUID_STD_CMPXCHG8B (1 << 8)
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#define BX_CPUID_STD_APIC (1 << 9)
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#define BX_CPUID_STD_RESERVED10 (1 << 10)
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#define BX_CPUID_STD_SYSENTER_SYSEXIT (1 << 11)
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#define BX_CPUID_STD_MTRR (1 << 12)
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#define BX_CPUID_STD_GLOBAL_PAGES (1 << 13)
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#define BX_CPUID_STD_MCA (1 << 14)
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#define BX_CPUID_STD_CMOV (1 << 15)
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#define BX_CPUID_STD_PAT (1 << 16)
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#define BX_CPUID_STD_PSE36 (1 << 17)
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#define BX_CPUID_STD_PROCESSOR_SERIAL_NUMBER (1 << 18)
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#define BX_CPUID_STD_CLFLUSH (1 << 19)
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#define BX_CPUID_STD_RESERVED20 (1 << 20)
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#define BX_CPUID_STD_DEBUG_STORE (1 << 21)
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#define BX_CPUID_STD_ACPI (1 << 22)
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#define BX_CPUID_STD_MMX (1 << 23)
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#define BX_CPUID_STD_FXSAVE_FXRSTOR (1 << 24)
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#define BX_CPUID_STD_SSE (1 << 25)
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#define BX_CPUID_STD_SSE2 (1 << 26)
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#define BX_CPUID_STD_SELF_SNOOP (1 << 27)
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#define BX_CPUID_STD_HT (1 << 28)
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#define BX_CPUID_STD_THERMAL_MONITOR (1 << 29)
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#define BX_CPUID_STD_RESERVED30 (1 << 30)
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#define BX_CPUID_STD_PBE (1 << 31)
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// CPUID defines - EXT features CPUID[0x00000001].ECX
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// ----------------------------
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// [0:0] SSE3: SSE3 Instructions
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// [1:1] PCLMULQDQ Instruction support
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// [2:2] DTES64: 64-bit DS area
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// [3:3] MONITOR/MWAIT support
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// [4:4] DS-CPL: CPL qualified debug store
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// [5:5] VMX: Virtual Machine Technology
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// [6:6] SMX: Secure Virtual Machine Technology
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// [7:7] EST: Enhanced Intel SpeedStep Technology
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// [8:8] TM2: Thermal Monitor 2
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// [9:9] SSSE3: SSSE3 Instructions
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// [10:10] CNXT-ID: L1 context ID
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// [11:11] reserved
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// [12:12] FMA Instructions support
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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// [14:14] xTPR update control
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// [15:15] PDCM - Perfon and Debug Capability MSR
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// [16:16] reserved
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// [17:17] PCID: Process Context Identifiers
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// [18:18] DCA - Direct Cache Access
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// [19:19] SSE4.1 Instructions
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// [20:20] SSE4.2 Instructions
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// [21:21] X2APIC
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// [22:22] MOVBE instruction
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// [23:23] POPCNT instruction
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// [24:24] TSC Deadline
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// [25:25] AES Instructions
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// [26:26] XSAVE extensions support
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// [27:27] OSXSAVE support
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// [28:28] AVX extensions support
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// [29:29] AVX F16C - Float16 conversion support
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// [30:30] RDRAND instruction
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// [31:31] reserved
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#define BX_CPUID_EXT_SSE3 (1 << 0)
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#define BX_CPUID_EXT_PCLMULQDQ (1 << 1)
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#define BX_CPUID_EXT_DTES64 (1 << 2)
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#define BX_CPUID_EXT_MONITOR_MWAIT (1 << 3)
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#define BX_CPUID_EXT_DS_CPL (1 << 4)
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#define BX_CPUID_EXT_VMX (1 << 5)
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#define BX_CPUID_EXT_SMX (1 << 6)
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#define BX_CPUID_EXT_EST (1 << 7)
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#define BX_CPUID_EXT_THERMAL_MONITOR2 (1 << 8)
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#define BX_CPUID_EXT_SSSE3 (1 << 9)
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#define BX_CPUID_EXT_CNXT_ID (1 << 10)
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#define BX_CPUID_EXT_RESERVED11 (1 << 11)
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#define BX_CPUID_EXT_FMA (1 << 12)
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#define BX_CPUID_EXT_CMPXCHG16B (1 << 13)
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#define BX_CPUID_EXT_xTPR (1 << 14)
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#define BX_CPUID_EXT_PDCM (1 << 15)
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#define BX_CPUID_EXT_RESERVED16 (1 << 16)
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#define BX_CPUID_EXT_PCID (1 << 17)
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#define BX_CPUID_EXT_DCA (1 << 18)
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#define BX_CPUID_EXT_SSE4_1 (1 << 19)
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#define BX_CPUID_EXT_SSE4_2 (1 << 20)
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#define BX_CPUID_EXT_X2APIC (1 << 21)
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#define BX_CPUID_EXT_MOVBE (1 << 22)
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#define BX_CPUID_EXT_POPCNT (1 << 23)
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#define BX_CPUID_EXT_TSC_DEADLINE (1 << 24)
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#define BX_CPUID_EXT_AES (1 << 25)
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#define BX_CPUID_EXT_XSAVE (1 << 26)
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#define BX_CPUID_EXT_OSXSAVE (1 << 27)
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#define BX_CPUID_EXT_AVX (1 << 28)
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#define BX_CPUID_EXT_AVX_F16C (1 << 29)
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#define BX_CPUID_EXT_RDRAND (1 << 30)
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#define BX_CPUID_EXT_RESERVED31 (1 << 31)
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// CPUID defines - EXT3 features CPUID[0x00000007].EBX
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// -----------------------------
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// [0:0] FS/GS BASE access instructions
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// [1:1] Support for IA32_TSC_ADJUST MSR
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// [2:2] reserved
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// [3:3] BMI1: Advanced Bit Manipulation Extensions
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// [4:4] HLE: Hardware Lock Elision
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// [5:5] AVX2
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// [6:6] reserved
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// [7:7] SMEP: Supervisor Mode Execution Protection
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// [8:8] BMI2: Advanced Bit Manipulation Extensions
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// [9:9] Support for Enhanced REP MOVSB/STOSB
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// [10:10] Support for INVPCID instruction
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// [11:11] RTM: Restricted Transactional Memory
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// [12:12] Supports Quality of Service (QoS) capability
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// [13:13] Deprecates FPU CS and FPU DS values
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// [14:14] Intel Memory Protection Extensions
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// [15:15] reserved
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// [16:16] AVX512F instructions support
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// [17:17] reserved
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// [18:18] RDSEED instruction support
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// [19:19] ADCX/ADOX instructions support
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// [20:20] SMAP: Supervisor Mode Access Prevention
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// [24:21] reserved
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// [25:25] Intel Processor Trace
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// [26:26] AVX512PF instructions support
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// [27:27] AVX512ER instructions support
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// [28:28] AVX512CD instructions support
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// [29:29] SHA instructions support
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// [31:30] reserved
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#define BX_CPUID_EXT3_FSGSBASE (1 << 0)
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#define BX_CPUID_EXT3_TSC_ADJUST (1 << 1)
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#define BX_CPUID_EXT3_RESERVED2 (1 << 2)
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#define BX_CPUID_EXT3_BMI1 (1 << 3)
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#define BX_CPUID_EXT3_HLE (1 << 4)
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#define BX_CPUID_EXT3_AVX2 (1 << 5)
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#define BX_CPUID_EXT3_RESERVED6 (1 << 6)
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#define BX_CPUID_EXT3_SMEP (1 << 7)
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#define BX_CPUID_EXT3_BMI2 (1 << 8)
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#define BX_CPUID_EXT3_ENCHANCED_REP_STRINGS (1 << 9)
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#define BX_CPUID_EXT3_INVPCID (1 << 10)
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#define BX_CPUID_EXT3_RTM (1 << 11)
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#define BX_CPUID_EXT3_QOS (1 << 12)
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#define BX_CPUID_EXT3_DEPRECATE_FCS_FDS (1 << 13)
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#define BX_CPUID_EXT3_MEMORY_PROTECTION_EXT (1 << 14)
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#define BX_CPUID_EXT3_RESERVED15 (1 << 15)
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#define BX_CPUID_EXT3_AVX512F (1 << 16)
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#define BX_CPUID_EXT3_RESERVED17 (1 << 17)
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#define BX_CPUID_EXT3_RDSEED (1 << 18)
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#define BX_CPUID_EXT3_ADX (1 << 19)
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#define BX_CPUID_EXT3_SMAP (1 << 20)
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#define BX_CPUID_EXT3_RESERVED21 (1 << 21)
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#define BX_CPUID_EXT3_RESERVED22 (1 << 22)
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#define BX_CPUID_EXT3_RESERVED23 (1 << 23)
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#define BX_CPUID_EXT3_RESERVED24 (1 << 24)
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#define BX_CPUID_EXT3_PROCESSOR_TRACE (1 << 25)
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#define BX_CPUID_EXT3_AVX512PF (1 << 26)
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#define BX_CPUID_EXT3_AVX512ER (1 << 27)
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#define BX_CPUID_EXT3_AVX512CD (1 << 28)
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#define BX_CPUID_EXT3_SHA (1 << 29)
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#define BX_CPUID_EXT3_RESERVED30 (1 << 30)
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#define BX_CPUID_EXT3_RESERVED31 (1 << 31)
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|
|
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// CPUID defines - STD2 features CPUID[0x80000001].EDX
|
|
// -----------------------------
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|
|
|
// ...
|
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#define BX_CPUID_STD2_SYSCALL_SYSRET (1 << 11)
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// ...
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#define BX_CPUID_STD2_NX (1 << 20)
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#define BX_CPUID_STD2_RESERVED21 (1 << 21)
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#define BX_CPUID_STD2_AMD_MMX_EXT (1 << 22)
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#define BX_CPUID_STD2_RESERVED23 (1 << 23)
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|
#define BX_CPUID_STD2_RESERVED24 (1 << 24)
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|
#define BX_CPUID_STD2_FFXSR (1 << 25)
|
|
#define BX_CPUID_STD2_1G_PAGES (1 << 26)
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|
#define BX_CPUID_STD2_RDTSCP (1 << 27)
|
|
#define BX_CPUID_STD2_RESERVED28 (1 << 28)
|
|
#define BX_CPUID_STD2_LONG_MODE (1 << 29)
|
|
#define BX_CPUID_STD2_3DNOW_EXT (1 << 30)
|
|
#define BX_CPUID_STD2_3DNOW (1 << 31)
|
|
|
|
// CPUID defines - EXT2 features CPUID[0x80000001].ECX
|
|
// -----------------------------
|
|
|
|
// [0:0] LAHF/SAHF instructions support in 64-bit mode
|
|
// [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD)
|
|
// [2:2] SVM: Secure Virtual Machine (AMD)
|
|
// [3:3] Extended APIC Space
|
|
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
|
|
// [5:5] LZCNT: LZCNT instruction support
|
|
// [6:6] SSE4A: SSE4A Instructions support
|
|
// [7:7] Misaligned SSE support
|
|
// [8:8] PREFETCHW: PREFETCHW instruction support
|
|
// [9:9] OSVW: OS visible workarounds (AMD)
|
|
// [10:10] IBS: Instruction based sampling
|
|
// [11:11] XOP: Extended Operations Support and XOP Prefix
|
|
// [12:12] SKINIT support
|
|
// [13:13] WDT: Watchdog timer support
|
|
// [14:14] reserved
|
|
// [15:15] LWP: Light weight profiling
|
|
// [16:16] FMA4: Four-operand FMA instructions support
|
|
// [18:17] reserved
|
|
// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
|
|
// [20:20] reserved
|
|
// [21:21] TBM: trailing bit manipulation instruction support
|
|
// [22:22] Topology extensions support
|
|
// [23:23] PerfCtrExtCore: core performance counter extensions support
|
|
// [24:24] PerfCtrExtNB: NB performance counter extensions support
|
|
// [25:25] Streaming performance monitor architecture.
|
|
// [26:26] Data breakpoint extension. Indicates support for MSR 0xC0011027 and MSRs 0xC001101[B:9].
|
|
// [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280.
|
|
// [31:28] reserved
|
|
|
|
#define BX_CPUID_EXT2_LAHF_SAHF (1 << 0)
|
|
#define BX_CPUID_EXT2_CMP_LEGACY (1 << 1)
|
|
#define BX_CPUID_EXT2_SVM (1 << 2)
|
|
#define BX_CPUID_EXT2_EXT_APIC_SPACE (1 << 3)
|
|
#define BX_CPUID_EXT2_ALT_MOV_CR8 (1 << 4)
|
|
#define BX_CPUID_EXT2_LZCNT (1 << 5)
|
|
#define BX_CPUID_EXT2_SSE4A (1 << 6)
|
|
#define BX_CPUID_EXT2_MISALIGNED_SSE (1 << 7)
|
|
#define BX_CPUID_EXT2_PREFETCHW (1 << 8)
|
|
#define BX_CPUID_EXT2_OSVW (1 << 9)
|
|
#define BX_CPUID_EXT2_IBS (1 << 10)
|
|
#define BX_CPUID_EXT2_XOP (1 << 11)
|
|
#define BX_CPUID_EXT2_SKINIT (1 << 12)
|
|
#define BX_CPUID_EXT2_WDT (1 << 13)
|
|
#define BX_CPUID_EXT2_RESERVED14 (1 << 14)
|
|
#define BX_CPUID_EXT2_LWP (1 << 15)
|
|
#define BX_CPUID_EXT2_FMA4 (1 << 16)
|
|
#define BX_CPUID_EXT2_RESERVED17 (1 << 17)
|
|
#define BX_CPUID_EXT2_RESERVED18 (1 << 18)
|
|
#define BX_CPUID_EXT2_NODEID (1 << 19)
|
|
#define BX_CPUID_EXT2_RESERVED20 (1 << 20)
|
|
#define BX_CPUID_EXT2_TBM (1 << 21)
|
|
#define BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS (1 << 22)
|
|
#define BX_CPUID_EXT2_PERFCTR_EXT_CORE (1 << 23)
|
|
#define BX_CPUID_EXT2_PERFCTR_EXT_NB (1 << 24)
|
|
#define BX_CPUID_EXT2_STREAMING_PERFMON (1 << 25)
|
|
#define BX_CPUID_EXT2_DATA_BREAKPOINT_EXT (1 << 26)
|
|
#define BX_CPUID_EXT2_PERF_TSC (1 << 27)
|
|
|
|
// CPUID defines - SVM features CPUID[0x8000000A].EDX
|
|
// ----------------------------
|
|
|
|
// [0:0] NP - Nested paging support
|
|
// [1:1] LBR virtualization
|
|
// [2:2] SVM Lock
|
|
// [3:3] NRIPS - Next RIP save on VMEXIT
|
|
// [4:4] TscRate - MSR based TSC ratio control
|
|
// [5:5] VMCB Clean bits support
|
|
// [6:6] Flush by ASID support
|
|
// [7:7] Decode assists support
|
|
// [8:8] Reserved
|
|
// [9:9] Reserved
|
|
// [10:10] Pause filter support
|
|
// [11:11] Reserved
|
|
// [12:12] Pause filter threshold support
|
|
// [13:13] Advanced Virtual Interrupt Controller
|
|
|
|
#define BX_CPUID_SVM_NESTED_PAGING (1 << 0)
|
|
#define BX_CPUID_SVM_LBR_VIRTUALIZATION (1 << 1)
|
|
#define BX_CPUID_SVM_SVM_LOCK (1 << 2)
|
|
#define BX_CPUID_SVM_NRIP_SAVE (1 << 3)
|
|
#define BX_CPUID_SVM_TSCRATE (1 << 4)
|
|
#define BX_CPUID_SVM_VMCB_CLEAN_BITS (1 << 5)
|
|
#define BX_CPUID_SVM_FLUSH_BY_ASID (1 << 6)
|
|
#define BX_CPUID_SVM_DECODE_ASSIST (1 << 7)
|
|
#define BX_CPUID_SVM_RESERVED8 (1 << 8)
|
|
#define BX_CPUID_SVM_RESERVED9 (1 << 9)
|
|
#define BX_CPUID_SVM_PAUSE_FILTER (1 << 10)
|
|
#define BX_CPUID_SVM_RESERVED11 (1 << 11)
|
|
#define BX_CPUID_SVM_PAUSE_FILTER_THRESHOLD (1 << 12)
|
|
#define BX_CPUID_SVM_AVIC (1 << 13)
|
|
|
|
#endif
|